MC14LC5540DW 데이터 시트보기 (PDF) - Motorola => Freescale

부품명

상세내역

제조사

MC14LC5540DW

ADPCM Codec

Motorola => Freescale 

In a sampling environment, Nyquist theory says that to

properly sample a continuous signal, it must be sampled at a

frequency higher than twice the signal’s highest frequency

component. Voice contains spectral energy above 3 kHz, but

its absence is not detrimental to intelligibility. To reduce the

digital data rate, which is proportional to the sampling rate, a

sample rate of 8 kHz was adopted, consistent with a band-

width of 3 kHz. This sampling requires a low–pass filter to

limit the high frequency energy above 3 kHz from distorting

the inband signal. The telephone line is also subject to

50/60 Hz power line coupling, which must be attenuated

from the signal by a high–pass filter before the analog–to–

digital converter.

The digital–to–analog conversion process reconstructs a

staircase version of the desired inband signal which has

spectral images of the inband signal modulated about the

sample frequency and its harmonics. These spectral images

are called aliasing components which need to be attenuated

to obtain the desired signal. The low–pass filter used to at-

tenuate these aliasing components is typically called a re-

construction or smoothing filter.

The MC14LC5540 ADPCM Codec incorporates this codec

function as one of its main functional blocks.

ADPCM TRANSCODER BLOCK DESCRIPTION

An Adaptive Differential PCM (ADPCM) transcoder is used

to reduce the data rate required to transmit a PCM encoded

voice signal while maintaining the voice fidelity and intel-

ligibility of the PCM signal.

The ADPCM transcoder is used on both Mu–Law and

A–Law 64 kbps data streams which represent either voice or

voice band data signals that have been digitized by a PCM

Codec–Filter. The PCM to ADPCM encoder section of this

transcoder has a type of linear predicting digital filter which is

trying to predict the next PCM sample based on the previous

history of the PCM samples. The ADPCM to PCM decoder

section implements an identical linear predicting digital filter.

The error or difference between the predicted and the true

PCM input value is the information that is sent from the en-

coder to the decoder as an ADPCM word. The characteris-

tics of this ADPCM word include the number of quantized

steps (this determines the number of bits per ADPCM word)

and the actual meaning of this word is a function of the pre-

dictor’s output value, the error signal and the statistics of the

history of PCM words. The term “adaptive” applies to the

transfer function of the filter that generates the ADPCM word

which adapts to the statistics of the signals presented to it.

This means that an ADPCM word “3” does not have the

same absolute error voltage weighting for the analog signal

when the channel is quiet as it does when the channel is pro-

cessing a speech signal. The ADPCM to PCM decoder sec-

tion has a reciprocating filter function which interprets the

ADPCM word for proper reconstruction of the PCM sample.

The adaptive characteristics of the ADPCM algorithm

make it difficult to analyze and quantify the performance of

the ADPCM code sequence. The 32 kbps algorithm was op-

vtimized for both voice and moderate speed modems

( 4800 baud). This optimization includes that the algorithm

supports the voice frequency band of 300 – 3400 Hz with

minimal degradation for signal–to–distortion, gain–versus–

level, idle channel noise, and other analog transmission per-

formance. This algorithm has also been subjected to

audibility testing with many languages for Mean Opinion

MC14LC5540

10

Score (MOS) ratings and performed well when compared to

64 kbps PCM. The standards committees have specified

multiple 16000 word test vectors for the encoder and for the

decoder to verify compliance. To run these test vectors, the

device must be initialized to the reference state by resetting

the device.

In contrast to 64 kbps PCM, the ADPCM words appear as

random bit activity on an oscilloscope display whether the

audio channel is processing speech or a typical PCM idle

channel with nominal bit activity. The ADPCM algorithm does

not support dc signals with the exception of digital quiet,

which will result in all ones in the ADPCM channel. All digital

processing is performed on 13–bit linearizations of the 8–bit

PCM companded words, whether the words are Mu–Law or

A–Law. This allows an ADPCM channel to be intelligibly de-

coded into a Mu–Law PCM sequence or an A–Law PCM se-

quence irrespective of whether it was originally digitized as

Mu–Law or A–Law. There will be additional quantizing degra-

dation if the companding scheme is changed because the

ADPCM algorithm is trying to reconstruct the original 13–bit

linear codes, which included companding quantization.

CHARGE PUMP

The charge pump is the functional block that allows the

analog signal processing circuitry of the MC14LC5540 to op-

erate with a power supply voltage as low as 2.7 V. This ana-

log signal processing circuitry includes the PCM

Codec–Filter function, the transmit trim gain, the receive trim

gain, the sidetone gain control, and the transmit input opera-

tional amplifier. This circuitry does not dissipate much current

but it does require a nominal voltage of 5 V for the VDD power

supply.

The charge pump block is a regulated voltage doubler

which takes twice the current it supplies from the voltage ap-

plied to the VEXT power supply pin which may range from 2.7

to 5.25 V and generates the required 5 V VDD supply. The

charge pump block receives as inputs the VEXT supply volt-

age, the same 256 kHz clock that sequences the analog sig-

nal processing circuitry, and the Charge Pump Enable signal

from the SCP block. It also makes use of the capacitor con-

nected to the C1+ and C1– pins and the decoupling capacitor

connected to the VDD pin.

FUNCTIONAL DESCRIPTION

POWER SUPPLY CONFIGURATION

Analog Signal Processing Power Supply

All analog signal processing is powered by the VDD pin at

5 V. This voltage may be applied directly to the VDD pin or

5 V may be obtained by the on–chip 5 V regulated charge

pump which is powered from the VEXT pin. The VEXT pin is

the main positive power supply pin for this device.

For applications that are not 5 V regulated, the on–chip 5 V

regulated charge pump may be turned on and C1 will be re-

quired. VDD will require a 1.0 µF decoupling capacitor to filter

the voltage spikes of the charge pump. This allows the VEXT

power supply to be from 2.7 to 5.25 V. This mode of opera-

tion is intended for hand held applications where three NiCad

cells or three dry cells would be the power supply.

The on–chip 5 V regulated charge pump is a single stage

charge pump that effectively series regulates the amount of

voltage it generates and internally applies this regulated

voltage to the VDD pin. This 5 V voltage is developed by

MOTOROLA

Share Link: