MC14LC5540DW 데이터 시트보기 (PDF) - Motorola => Freescale

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MC14LC5540DW

ADPCM Codec

Motorola => Freescale 

BCLKR

Bit Clock, Receive (PDIP, SOG, TQFP—Pin 26)

When used in the Long Frame Sync or Short Frame Sync

mode, this pin accepts any bit clock frequency from 64 to

5120 kHz. This pin may be used for applying an external

256 kHz clock for sequencing the analog signal processing

functions of this device. This is selected by the SCP port at

BR0 (b7).

FSR

Frame Sync, Receive (PDIP, SOG, TQFP—Pin 27)

When used in the Long Frame Sync or Short Frame Sync

mode, this pin accepts an 8 kHz clock that synchronizes the

input of the serial ADPCM data at the DR pin. FSR can oper-

ate asynchronous to FST in the Long Frame Sync or Short

Frame Sync mode.

SERIAL CONTROL PORT INTERFACE PINS

PDI/RESET

Power–Down Input/Reset

(PDIP, SOG—Pin 13; TQFP—Pin 11)

A logic 0 applied to this input forces the device into a low–

power dissipation mode. A rising edge on this pin causes

power to be restored and the ADPCM Reset state (specified

in the standards) to be forced.

SCPEN

Serial Control Port Enable Input

(PDIP, SOG—Pin 14; TQFP—Pin 12)

This pin, when held low, selects the Serial Control Port

(SCP) for the transfer of control and status information into

and out of the MC14LC5540 ADPCM Codec. This pin should

be held low for a total of 16 periods of the SCPCLK signal in

order for information to be transferred into or out of the

MC14LC5540 ADPCM Codec. The timing relationship be-

tween SCPEN and SCPCLK is shown in Figures 6 through 9.

SCPCLK

Serial Control Port Clock Input

(PDIP, SOG—Pin 15; TQFP—Pin 13)

This input to the device is used for controlling the rate of

transfer of data into and out of the SCP Interface. Data are

clocked into the MC14LC5540 ADPCM Codec from SCP Rx

on rising edges of SCPCLK. Data are shifted out of the de-

vice on SCP Tx on falling edges of SCPCLK. SCPCLK can

be any frequency from 0 to 4.096 MHz. An SCP transaction

takes place when SCPEN is brought low. Note that SCPCLK

is ignored when SCPEN is high ( i.e., it may be continuous or

it can operate in a burst mode).

SCP Tx

Serial Control Port Transmit Output

(PDIP, SOG—Pin 16; TQFP—Pin 14)

SCP Tx is used to output control and status information

from the MC14LC5540 ADPCM Codec. Data are shifted out

of SCP Tx on the falling edges of SCPCLK, most significant

bit first.

SCP Rx

Serial Control Port Receive Input

(PDIP, SOG—Pin 17; TQFP—Pin 15)

SCP Rx is used to input control and status information to

the MC14LC5540 ADPCM Codec. Data are shifted into the

device on rising edges of SCPCLK. SCP Rx is ignored when

data are being shifted out of SCP Tx or when SCPEN is

high.

MOTOROLA

MC14LC5540

5

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