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MC14LC5540DW

ADPCM Codec

Motorola => Freescale 

SCPEN

ÇÇÇ SCPCLK

ÇÇÇÇÇÇÇÇÇ SCP Rx

R/W

A3 A2 A1 AÇÇ0 ÇÇÇÇÇÇÇÇÇÇÇÇDÇÇON’TÇÇCARÇÇE ÇÇÇÇÇÇÇÇDOÇÇÇÇN’TÇÇCÇÇAREÇÇÇÇÇÇÇÇ

SCP Tx

HIGH IMPEDANCE

D7 D6 D5 D4 D3 D2 D1 D0

Figure 9. SCP Byte Register Read Operation Using Single 16–Bit Transfer

SERIAL CONTROL PORT (SCP) INTERFACE

The MC14LC5540 is equipped with an industry standard

Serial Control Port (SCP) Interface. The SCP is used by an

external controller, such as an M68HC05 family micro-

controller, to communicate with the MC14LC5540 ADPCM

Codec.

The SCP is a full–duplex, four–wire interface used to pass

control and status information to and from the ADPCM

Codec. The SCP Interface consists of a transmit output, a

receive input, a data clock, and an enable signal. These

device pins are known as SCP Tx, SCP Rx, SCPCLK, and

SCPEN, respectively. The SCPCLK determines the rate of

exchange of data in both the transmit and receive directions,

and the SCPEN signal governs when this exchange is to

take place.

The operation and configuration of the ADPCM Codec is

controlled by setting the state of the control and status regis-

ters within the MC14LC5540 and then monitoring these con-

trol and status registers. The control and status registers

reside in sixteen 8–bit wide Byte Registers, BR0 – BR15. A

complete register map can be found in the Serial Control

Port Registers section.

BYTE REGISTER OPERATIONS

The sixteen byte registers are addressed by addressing a

four–bit byte register address (A3:A0) as shown in Figures 6

and 7. A second 8–bit operation transfers the data word

(D7:D0). Alternatively, these registers can be accessed with

a single 16–bit operation as shown in Figures 8 and 9.

ADPCM CODEC DEVICE DESCRIPTION

The MC14LC5540 is a single channel Mu–Law or A–Law

companding PCM Codec–Filter with an ADPCM encoder/de-

coder operating on a single voltage power supply from 2.7 to

5.25 V.

The MC14LC5540 ADPCM Codec is a complete solution

for digitizing and reconstructing voice in compliance with

CCITT G.714, G.721–1988, G.723–1988, G.726, and ANSI

T1.301 and T1.303 for 64, 32, 24, and 16 kbps. This device

satisfies the need for high–quality, low–power, low data rate

voice transmission, and storage applications and is offered in

three plastic packages: the 28–pin DIP and 28–pin SOIC di-

rectly replace the MC145540, and the 32–pin TQFP (Thin

Quad Flat Package) is a new addition.

Referring to Figure 10, the main functional blocks of the

MC14LC5540 are the switched capacitor technology PCM

Codec–Filter, the DSP based ADPCM encoder/decoder, and

the voltage regulated charge pump. As an introduction to the

functionality of the ADPCM Codec, a basic description of

these functional blocks follows.

PCM CODEC–FILTER BLOCK DESCRIPTION

A PCM Codec–Filter is a device used for digitizing and re-

constructing the human voice. These devices were devel-

oped primarily for the telephone network to facilitate voice

switching and transmission. Once the voice is digitized, it

may be switched by digital switching methods or transmitted

long distance (T1, microwave, fiber optics, satellites, etc.)

without degradation. The name codec is an acronym from

“COder” for the analog–to–digital converter (ADC) used to

digitize voice, and “DECoder” for the digital–to–analog con-

verter (DAC) used for reconstructing voice. A codec is a

single device that does both the ADC and DAC conversions.

To digitize voice intelligibly requires a signal to distortion of

about 30 dB for a dynamic range of about 40 dB. This may be

accomplished with a linear 13–bit ADC and DAC, but will far

exceed the required signal to distortion at amplitudes greater

than 40 dB below the peak amplitude. This excess perfor-

mance is at the expense of bits of data per sample. Two

methods of data reduction are implemented by compressing

the 13–bit linear scheme to companded 8–bit schemes.

These companding schemes follow a segmented or “piece-

wise–linear” curve formatted as sign bit, three chord bits, and

four step bits. For a given chord, all 16 of the steps have the

same voltage weighting. As the voltage of the analog input

increases, the four step bits increment and carry to the three

chord bits, which increment. When the chord bits increment,

the step bits double their voltage weighting. This results in an

effective resolution of six bits (sign + chord + four step bits)

across a 42 dB dynamic range (seven chords above 0, by

6 dB per chord). There are two companding schemes used:

Mu–255 Law specifically in North America and A–Law

specifically in Europe. These companding schemes are

accepted world wide.

MC14LC5540

8

MOTOROLA

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