SN74LS259 데이터 시트보기 (PDF) - ON Semiconductor

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SN74LS259

8-Bit Addressable Latch

ON Semiconductor 

SN74LS259

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC C

E D Q7 Q6 Q5 Q4

16 15 14 13 12 11 10 9

1 2 3 4 56 78

Ao A1 A2 Q0 Q1 Q2 Q3 GND

PIN NAMES

A0, A1, A2

D

E

C

Q0 - Q7

Address Inputs

Data Input

Enable (Active LOW) Input

Clear (Active LOW) Input

Parallel Latch Outputs

NOTES:

ąa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

1.0 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.5 U.L.

0.25 U.L.

5 U.L.

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