LA9242M 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LA9242M

Analog Signal Processor (ASP) for CD Players

SANYO -> Panasonic 

LA9242M

11. DEFECT

The mirrored surface level is maintained by the capacitor for LF2 (pin 59) ; when a drop in the EFM signal (RFSM

output) reaches 0.35V or more, a high signal is output to DEF (pin 49). If DEF (pin 49) goes high, the tracking

servo enters THLD mode. In order to prevent the tracking servo from entering THLD mode when a defect is

detected, prevent DEFECT from being output by either shorting DEF (pin 49) to GND, or shorting LF2 (pin 59) to

GND. The DEFECT output is driven by constant current (approximately 100µA).

EFM signal

(RFSM output)

LF2 (pin 59)

0.35V

DEF (pin 59)

12. Microcontroller interface

Because the Reset (Nothing) command initializes the LA9242M, it must be used carefully.

The LA9242M command acceptance (mode switching) timing is defined by the internal clock (4.23MHz divided to

130kHz) after the falling edge of CE (RWC) ; therefore, when commands are sent consecutively, CE must go low

for at least 10µs. The 4.23MHz clock is required for that reason. 2BYTE-COMMAND DETECT and 2BYTE-

COMMAND RESET are used only for the purpose of masking two-byte data.

All instructions can be input by setting CE high and sending commands synchronized with the CL clock from the

microcontroller to DAT (pin 52) in LSB first format. Note that the command is executed at the falling edge of CE.

Timing

CE(RWC)

CL(CQCK)

DAT(COIN)

LSB

MSB

* The DSP pin names are shown in parentheses.

13. Reset circuit

The power-on reset is released when VCC exceeds approximately 2.6V.

14. Pattern design notes

To prevent signal jump-in from CV+ (pin 40) to RFSM (pin 41), a shielding line is necessary in between.

15. VCC /REF/GND/NC

VCC1 (pin 64)

: RF system

VCC2 (pin 56)

: SERVO system, DIGITAL system

AGND (pin 22) : RF system, SERVO system

DGND (pin 45) : DIGITAL system

NC (pin 23, 48) : No connection

VR (pin 58)

: Refered voltage

No.7097–9/20

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