W88111AF 데이터 시트보기 (PDF) - Winbond
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W88111AF Datasheet PDF : 64 Pages
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W88111AF/W88112F
ATAPI CD-ROM Decoder & Controller
This specification is subject to change without notice.
Preliminary/Confidential
UINTb
36
OD Microprocessor Interrupt - A signal can be externally wired-OR
with other interrupt sources.
Host Interface
NAME
NO.
DD[15:0]
54, 56, 59, 62,
65, 68, 70, 73,
74, 71, 69, 67,
63, 61, 57, 55
DA[2:0]
40, 44, 42
DASPb
37
CS3b
38
CS1b
39
PDIAGb
43
IOCS16b
45
HIRQ
47
DMACKb
48
IORDY
49
HRDb
50
HWRb
52
DMARQ
53
TYPE
I/OZ
I
I/OD
I
I
I/OD
OD
OZ
I
OZ
I
I
OZ
PIN DESCRIPTION
Host Data Bus - Signals enable data transfer between the host
and W88111AF/W88112F.
Host Address Bus - Signals to access various ATAPI registers.
Drive Active/Drive 1 Present - A time-multiplexed signal
indicating whether a drive is active, or Drive 1 is present.
Host Chip Select 1 - A signal used to select the host Control
Block Registers.
Host Chip Select 0 - A signal used to select the host Command
Block Registers.
Passed Diagnostics - A signal asserted by Drive 1 to indicate to
Drive 0 that diagnostics is completed.
16-bit I/O Select - During PIO transfer, this signal becomes
active-high to indicate a 16-bit data transfer.
Host Interrupt - A signal to request an interrupt service from
host.
DMA Acknowledge - A signal used for DMA transfer by the host
when DMARQ is ready.
I/O Channel Ready - When W88111AF/W88112F is not ready
for a data transfer request, this signal is negated for extension of
the host data transfer cycle within any host register access.
Host I/O Read - The read strobe signal.
Host I/O Write - The write strobe signal.
DMA Request - A signal asserted for DMA data transfer when
W88111AF/W88112F is ready to transfer data to or from the
host.
ATAPI Register Definition
CS1b
ADDRESSES
CS3b
DA2
DA1
DA0
Read
Control block registers
FUNCTIONS
Write
N
A
1
1
0
Alternate status
Device control
Publication Release Date: Aug, 1996
-9-
Preliminary/ Confidential Revision A0.1
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