MC92500ZQ 데이터 시트보기 (PDF) - Motorola => Freescale

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MC92500ZQ

ATM Cell Processor

Motorola => Freescale 

2. FUNCTIONAL DESCRIPTION

2.1 System Functional Description

A serial transmission link operating at up to 155.52Mbit/

sec (PHY) is coupled to the MC92500 via a byte-based

interface. The transmission link timing is adapted to the

MC92500 and switch timing by means of internal FIFO

cell buffers. A common clock is used to supply both the

PHY-IF and MC92500.

The host microprocessor initializes and provides real-

time control of the data-flow chips (PHY-IF and

MC92500) using slave accesses.

The MC92500 operates in conjunction with an external

connection memory, which provides one context entry

for each active connection. The entry consists of two

types of context parameters: static and dynamic. The

static parameters are loaded into the context memory

when the VC is established, and are valid for the dura-

tion of that connection. Included in the static parame-

ters are traffic descriptors, OAM flags and parameters

used by the ATM switch. The dynamic context parame-

ters, which include cell counters, UPC/NPC fields and

OAM parameters, may be modified as cells belonging

to that particular connection are processed by the

MC92500. The microprocessor also accesses the ex-

ternal memory through the MC92500 from time to time

to collect traffic statistics and to update the OAM pa-

rameters. During normal cell processing, the MC92500

has exclusive access to the external memory. The con-

text entries for the cells being processed are read and

the updated dynamic parameters are written back. The

MC92500 is responsible for the coherency of the exter-

nal memory during this time.

At user-programmable intervals the MC92500 provides

the microprocessor with a “maintenance slot”, during

which no cell processing is done, and relinquishes the

external memory bus. The break in cell processing is

made possible by the difference between the MC92500

cell-processing rate and the line rate.

The maintenance slot shall be used by the micropro-

cessor for one or more of the following tasks:

• Connection setup and tear down

• Statistics collection

• Updating OAM parameters of active

connection

The microprocessor is responsible for the coherency of

the external memory at the end of each maintenance

slot.

2.2 MC92500 Functional Description

MC92500 General Features

• Implements ATM Layer functions for Broadband

ISDN according to CCITT recommendations and

ATM forum user network interface specifications

• Provides a throughput capacity of up to 155 Mbit/

sec in each direction

• Processes ATM cells from a SONET STS-3c,

SONET STS-1, DS3 PLCP, or any other physical

link running at up to 155 Mbit/sec

• Optionally supports up to 16 physical links

• Optionally configured as a User Network Interface

(UNI) or Network Node Interface (NNI) on a per-link

basis

• Operates in conjunction with an external memory

(up to 16 MB) to provide context management for

up to 64K Virtual Connections

• Provides explicit bank select signals to support up

to four banks of external memory

• Provides per-connection cell counters with the abil-

ity to maintain multiple copies of the counter tables

and dynamically switch between them

• Provides per-link cell counters in both directions

• Provides per-connection Usage Parameter Control

(UPC) or Network Parameter Control (NPC) using

a leaky bucket design with up to four buckets per

connection

• Provides support for Operation and Maintenance

(OAM) Continuity Check function for all connec-

tions

• Supports Virtual Path (VP) and Virtual Channel

(VC) level Alarm Surveillance on all connections

using an internal scan process to generate and

insert OAM cells

• Supports OAM Fault Management Loopback test

on all connections

• Supports bidirectional OAM Performance Monitor-

ing on up to 64 connections

• Provides a slave microprocessor interface includ-

ing a 32-bit data bus

• Provides byte-swapping on cell payloads to and

from the microprocessor bus in order to support

both big-endian and little-endian buses

• Supports cell insertion into the cell streams using

direct access registers which may be written by the

microprocessor or by a DMA device

• Supports copying cells from the cell streams using

direct access registers which may be read by the

microprocessor or by a DMA device

• Supports multicast operation

MC92500

MOTOROLA

5

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