UPD98401AGD-MML 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

µPD98401A

Pin Name

Pin No.

I/O

I/O Level

Function

(2/3)

DR/W_B

62

O

CMOS

DMA Read/Write.

DR/W_B indicates the direction of DMA access.

1: Read access

0: Write access

This pin is set to 1 after reset.

ATTN_B

63

O

CMOS

Attention/Burst Frame (DMA request).

The µPD98401A makes the ATTN_B signal low when it performs a

DMA operation. The ATTN_B signal becomes inactive at the rising

edge of CLK when the data to be transferred by means of DMA has

decreased to 1 word.

GNT_B

64

I

TTL

Grant.

The GNT_B signal inputs a low level when the bus arbiter grants the

µPD98401A use of the bus in response to a DMA request from the

µPD98401A. The µPD98401A recognizes that it has been granted

use of the bus and starts DMA operation when the GNT_B signal goes

low (active). Make sure that the GNT_B signal falls at least one

system clock cycle after the rising of the ATTN_B signal. The GNT_B

signal must be returned to the high (inactive) level before the

µPD98401A makes the ATTN_B signal low (active) to issue the next

DMA cycle request.

RDY_B

65

I

TTL

Target Ready.

RDY_B indicates to the µPD98401A in the DMA cycle that the target

device is ready for input/output. During the DMA read operation of the

µPD98401A, the RDY_B signal is made low if valid data is on AD31

through AD0.

During the DMA write operation of the µPD98401A, the RDY_B signal

is made low if the target device is ready for receiving data.

The sampling timing of the RDY_B and ABRT_B signals of the

µPD98401A can be advanced by one clock (early mode) by using an

internal register (GMR register).

ABRT_B

66

I

TTL

Abort.

ABRT_B is used to abort the DMA transfer cycle. If this signal goes

low while data is being transferred in the DMA cycle, DMA transfer is

aborted in that cycle, and the ATTN_B signal is briefly deasserted

inactive. After that, the µPD98401A asserts the ATTN_B signal active

again, and resumes burst transfer from the data at which the DMA

transfer was aborted. While a low level is input to ABRT_B, the

RDY_B signal is ignored. The user can advance the sampling timing

of the RDY_B and ABRT_B signals of the µPD98401A by one clock

(early mode) by using an internal register (GMR register). Pull up this

pin when it is not used.

ERR_B

67

I

TTL

Error.

This pin is used by a device that manages the bus to stop the

operation of the µPD98401A when occurrence of an error is detected

on the system bus.

When a low level is input to this pin, the µPD98401A stops all bus

operations, sets the system bus error bit (bit 25) of the GSR register

(when not masked), and generates an interrupt. Pull up this pin when

it is not used.

10

Data Sheet S12100EJ3V0DS00

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