UPD98401AGD-MML 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD98401AGD-MML

ATM SAR CHIP

NEC => Renesas Technology 

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD98401A

ATM SAR CHIP

DESCRIPTION

The µPD98401A (NEASCOT-S15TM) is a high-performance SAR chip that segments and reassembles ATM cells.

This chip can interface with an ATM network when it is included in a workstation, computer, front-end processor,

network hub, or router. The µPD98401A conforms to the ATM Forum Recommendation, and provides the functions

of the AAL-5 SAR sublayer and ATM layer.

The µPD98401A is compatible with its predecessor, µPD98401, in terms of hardware and software.

Functions are explained in detail in the following User’s Manual. Be sure to read this manual when designing your

system.

µPD98401A User’s Manual: S12054E

FEATURES

• Conforms to ATM Forum

• AAL-5 SAR sublayer and ATM layer functions

• Hardware support of AAL-5 processing

• Processing of non-AAL-5 traffic (AAL-3/4 cell, OAM cell, RM cell) by software with raw cell processing function

• Hardware support of comparison/generation of CRC-10 for non-AAL-5 traffic

• Supports up to 32K virtual channels (VC)

• Provided with 16 traffic shapers that carry out transmission scheduling (control of average rate/peak rate) so as to

set different transmission rate for each VC

• Interface and commands for controlling PHY device

• Employs “UTOPIA interface” as cell data interface with PHY device

- Octet-level handshake

- Cell-level handshake

• 32-bit general-purpose bus interface

• High-speed DMAC (supports 1-, 2-, 4-, 8-, 12-, and 16-word burst)

• JTAG boundary scan test function (IEEE1149.1)

• CMOS technology

• +5 V single power source

Remark In this document, an active low pin is indicated by ×××_B (_B after a pin name).

The information in this document is subject to change without notice.

Document No. S12100EJ3V0DS00 (3rd edition)

The mark shows major revised points.

Date Published February 1999 N CP(K)

©

Printed in Japan

1997

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