VSC8110GB 데이터 시트보기 (PDF) - Vitesse Semiconductor

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VSC8110GB

ATM/SONET/SDH 155/622 Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

VITESSE

VSC8110

Data Sheet

ATM/SONET/SDH 155/622 Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

down resistor should be placed as close to the VSC8110 pin as possible while the AC-coupling capacitor and

the biasing resistors should be placed as close as possible to the optics input pin. The same is true on the receive

circuit side. Using small outline components and minimum pad sizes also helps in reducing discontinuities.

Ground Planes

The ground plane for the components used in the 622 interface should be continuous and not sectioned in

an attempt to provide isolation to various components. Sectioning of the ground planes tends to interfere with

the ground return currents on the signal lines as well as in general, the smaller the ground planes the less effec-

tive they are in reducing ground bounce noise and the more difficult to decouple etc. Sectioning of the positive

supplies can provide some isolation benefits.

Reference Clock Generation

It has been noted that additional jitter may be generated on the reference clock if a TTL Oscillator is level

shifted using a TTL to ECL converter. The best recommendation is to use an ECL oscillator which can be AC-

coupled straight into the REF CLOCK inputs on the VSC8110

.

Figure 7: AC Coupled High Speed I/O

PECL

Output

+ 5 Volt Supply

Driver

C1

R1

VCC Ground

VSC8110

VECL

Input/Output

PECL

Input

VMM +2 Volt Supply

+ 5 Volt Supply

R2

C2

Receiver Driver

R5

C3

C4

Receiver

R3

R4

R6

VCC Ground

VCC Ground

Table 18: AC Coupling Component Values

Component

R1

R2

R3

R4

R5

R6

C1, C2, C3, C4

Value

270 ohms

147 ohms

76 ohms

50 - 100 ohms

68 ohms

190 ohms

.01uf High Frequency

Tolerance

1%

1%

1%

1%

1%

1%

G51011-0, Rev. 1.5

® VITESSE Semiconductor Corporation

Page 19

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