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FX806A 데이터 시트보기 (PDF) - CML Microsystems Plc

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FX806A
CML
CML Microsystems Plc CML
FX806A Datasheet PDF : 13 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Modulator Levels
Setting
Byte 1
MSB
7
6
5
0
0
0
43210
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Byte 0
MSB
7
6
5
0
0
0
43210
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
(Preceded by A/C12H)
Modulator Drives
First byte for transmission
Must be “0”
Mod. 1 Attenuation
12.4dB
12.0dB
11.6dB
11.2dB
10.8dB
10.4dB
10.0dB
9.6dB
9.2dB
8.8dB
8.4dB
8.0dB
7.6dB
7.2dB
6.8dB
6.4dB
6.0dB
5.6dB
5.2dB
4.8dB
4.4dB
4.0dB
3.6dB
3.2dB
2.8dB
2.4dB
2.0dB
1.6dB
1.2dB
0.8dB
0.4dB
0dB
Last byte for transmission
Must be “0”
Mod. 2 Attenuation
6.2dB
6.0dB
5.8dB
5.6dB
5.4dB
5.2dB
5.0dB
4.8dB
4.6dB
4.4dB
4.2dB
4.0dB
3.8dB
3.6dB
3.4dB
3.2dB
3.0dB
2.8dB
2.6dB
2.4dB
2.2dB
2.0dB
1.8dB
1.6dB
1.4dB
1.2dB
1.0dB
0.8dB
0.6dB
0.4dB
0.2dB
0dB
Volume Set
Setting
MSB
7
6
0
0
0
1
5
0
1
43210
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Table 5 Volume Set
(Preceded by A/C13H)
Volume Set
Transmitted First
Main Process Out
Enabled
Biased
Powersave
Chip Enabled
Powersaved
Volume Set Attenuation
Off
48.0dB
46.4dB
44.8dB
43.2dB
41.6dB
40.0dB
38.4dB
36.8dB
35.2dB
33.6dB
32.0dB
30.4dB
28.8dB
27.2dB
25.6dB
24.0dB
22.4dB
20.8dB
19.2dB
17.6dB
16.0dB
14.4dB
12.8dB
11.2dB
9.6dB
8.0dB
6.4dB
4.8dB
3.2dB
1.6dB
0dB
Command Loading Address/Commands and data bytes
must be loaded in accordance with the information given in
Figure 6 (Timing ).
The Powersave function is instigated by bit 5 of the
Volume Set Command (Table 5).
During Powersave, all internal elements except the Clock
Generator and “C-BUS” Interface are off, with the Mic Op-
Amp and Output Drive stage outputs connected to V .
SS
Modulator Drives are controlled separately, but the whole
two-byte Modulator Drive command must be loaded for each
required adjustment.
Chip Select must be held at a logic “1” for the period
“t ” between transactions.
CSOFF
Table 4 Modulator Drive Levels
8

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