CMX624 데이터 시트보기 (PDF) - MX-COM Inc

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CMX624

Bell 202 and V.23 Modem with Call Progress and DTMF

MX-COM Inc  

Bell 202 and V.23 Compatible Modem

13

CMX624 Preliminary Information

4.13 Tx/Rx UART

This block connects the µC, via the Serial Bus interface, to the received data from the FSK Demodulator and

to the transmit data input to the FSK Modulator.

As part of this function, the block can be programmed to convert data to be transmitted from 7 or 8-Bit bytes

to asynchronous data characters, adding Start and Stop bits and - optionally - a parity bit to the data before

passing it to the FSK Modulator. Similarly, in the receive direction it can extract data bits from asynchronous

characters coming from the FSK Demodulator, stripping off the Start and Stop bits and performing an optional

Parity check on the received data before passing the result over the Serial Bus to the µC. Bits 0-3 of the

SETUP Register control the number of Stop and Data bits and the Parity options for both receive and transmit

directions.

Data to be transmitted should be loaded by the µC into the TX DATA Register when the Tx Data Ready bit

(Bit 0) of the FLAGS Register goes high. It will then be treated by the Tx UART block in one of two ways,

depending on the setting of Bit 3 of the FSK MODE Register:

1. If the bit is ‘0’ (‘Tx Sync’ mode) then the 8 bits from the TX DATA Register will be transmitted sequentially

at 75bps, 150bps, or 1200bps, LSB (D0) first.

2. If Bit 3 of the FSK MODE Register is ‘1’ (‘Tx Async’) then bits will be transmitted as asynchronous data

characters at 75bps, 150bps, or 1200bps according to the following format:

A. One Start bit (Space).

B. 7 or 8 Data bits from the TX DATA Register (D0-D6 or D0-D7) as determined by Bit 0 of the

SETUP Register. LSB (D0) transmitted first.

C. Optional Parity bit (even or odd parity) as determined by Bits 1 and 2 of the SETUP Register.

D. One or Two Stop bits (Mark) as determined by Bit 3 of the SETUP Register.

In both cases data will only be transmitted if Bit 1 of the FSK MODE Register is set to ‘1’.

Failure to load the TX DATA Register with a new value when required will result in Bit 1 (Tx Data Underflow)

of the FLAGS Register being set to ‘1’ and if the ‘Tx Async’ mode of operation had been selected then a

continuous Mark (‘1’) signal will then be transmitted until a new value is loaded into TX DATA, whereas in ‘Tx

Sync’ mode the byte already in the TX DATA Register will be re-transmitted.

Tx FSK signal:

TTBD

TX DATA Register loaded:

Start D0 D1 D2 D3 D4 D5 D6 D7 P'ty Stop Start D0

TTBD

Tx Data Ready flag bit:

Tx Data Underflow flag bit:

TTBD

Figure 10: Transmit UART Function (Async)

©1999 MX-COM, Inc.

www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480180.108

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA

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