SSD1858 데이터 시트보기 (PDF) - Unspecified

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SSD1858

LCD Segment / Common Driver with Controller CMOS

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6.10 RVSS

Ground reference of Vref.

6.11 CVSS

Ground reference of analog circuitry.

6.12 VSS

Ground reference of logic circuitry.

6.13 VCI

Reference voltage input for internal DC-DC converter. The voltage of generated VCC equals to the

multiple factor (2X, 3X, 4X or 5X) times VCI with respect to VSS.

Note: Voltage at this input pin must be larger than or equal to VDD.

6.14 Vout

This is the most positive voltage supply pin of the chip. It can be supplied externally or generated by

the internal regulator.

6.15 VL5, VL4, VL3 and VL2

LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They

have the following relationship:

Vout > VL5 > VL4 > VL3 > VL2 > VSS

Table 4 - Vout > VL5 > VL4 > VL3 > VL2 > VSS Relationship

1 : a bias

VL5

(a-1)/a * Vout

VL4

(a-2)/a * Vout

VL3

2/a * Vout

VL2

1/a * Vout

a is equals to 9 at POR.

6.16 COM0 – COM63

These pins provide the row driving signal COM0 - COM63 to the LCD panel. See figure 5 and figure 6

about the COM signal mapping in different multiplex ratio N.

6.17 ICONS

This pin is the special icons line COM signal output.

6.18 COL0 – COL103

These pins provide the LCD column driving signal. Their voltage level is VSS during sleep mode.

6.19 CL

This pin is the external clock input for the device which is enabled by using an extended command.

Under normal operation, this pin should be left opened and internal oscillator will be used after power

on reset.

SSD1858

Rev 1.1

09/2002

10

SOLOMON

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