SSD1858 데이터 시트보기 (PDF) - Unspecified

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SSD1858

LCD Segment / Common Driver with Controller CMOS

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7.4 MPU Serial 4-wire Interface

The serial interface consists of serial clock SCK, serial data SDA, D/C# and CS#. SDA is shifted

into an 8-bit shift register on every rising edge of SCL in the order of D7, D6, ... D0. D/C# is

sampled on every eighth clock and the data byte in the shift register is written to the Display

Data RAM or command register in the same clock. No extra clock or command is required to

end the transmission.

7.5 MPU Serial 3-wire interface

Operation is similar to 4-wire serial interface while D/C# is not been used. The Display Data

Length instruction is used to indicate that a specified number display data byte(s) (1-256) are to

be transmitted. Next byte after the display data string is handled as a command.

It should be noted that if there is a signal glitch at SCK that causing an out of synchronization in

the serial communication, a hardware reset pulse at RES# pin is required to initialize the chip

for re-synchronization.

Table 6 -Modes of Operation

6800 Parallel

Data Read

Yes

Data Write

Yes

Command Read Status only

Command Write Yes

8080 Parallel

Yes

Yes

Status only

Yes

Serial

No

Yes

No

Yes

7.6 Graphic Display Data RAM (GDDRAM)

The GDDRAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of

the RAM is 104 x 65 x 2 = 13,520bits. Figure 5 is a description of the GDDRAM address map.

For mechanical flexibility, re-mapping on both Segment and Common outputs are provided.

For vertical scrolling of display, an internal register storing the display start line can be set to

control the portion of the RAM data mapped to the display. Figure 5 shows the case in which

the display start line register is set at 30H.

For those GDDRAM out of the display common range, they could still be accessed, for either

preparation of vertical scrolling data or even for the system usage.

7.7 Oscillator Circuit

This module is an On-Chip low power RC oscillator circuitry (Figure 4). The oscillator generates

the clock for the DC-DC voltage converter. This clock is also used in the Display Timing

Generator.

enable

Oscillation Circuit

Oscillator

enable

enable

Buffer

(CL)

13

SSD1858

OSC1

Rev 1.1

09/2002

Internal Resistor

OSC2

Figure 4 - Oscillator Circuitry

SOLOMON

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