SST25VF512A 데이터 시트보기 (PDF) - Silicon Storage Technology

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SST25VF512A

512 Kbit SPI Serial Flash

Silicon Storage Technology 

512 Kbit SPI Serial Flash

SST25VF512A

Block Protection (BP1, BP0)

The Block-Protection (BP1, BP0) bits define the size of the

memory area, as defined in Table 5, to be software pro-

tected against any memory Write (Program or Erase)

operations. The Write-Status-Register (WRSR) instruction

is used to program the BP1 and BP0 bits as long as WP#

is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase

can only be executed if Block-Protection bits are both 0.

After power-up, BP1 and BP0 are set to 1.

Block Protection Lock-Down (BPL)

WP# pin driven low (VIL), enables the Block-Protection-

Lock-Down (BPL) bit. When BPL is set to 1, it prevents any

further alteration of the BPL, BP1, and BP0 bits. When the

WP# pin is driven high (VIH), the BPL bit has no effect and

its value is “Don’t Care”. After power-up, the BPL bit is

reset to 0.

Data Sheet

TABLE 5: SOFTWARE STATUS REGISTER

BLOCK PROTECTION1

Protection Level

Status

Register Bit

BP1 BP0

Protected

Memory Area

0

0

0

None

1

0

(1/4 Memory Array)

1 0C000H-0FFFFH

2

1

(1/2 Memory Array)

0 08000H-0FFFFH

3

1

(Full Memory Array)

1 00000H-0FFFFH

1. Default at power-up for BP1 and BP0 is ‘11’.

T5.0 1264

Auto Address Increment (AAI)

The Auto Address Increment Programming-Status bit pro-

vides status on whether the device is in AAI programming

mode or Byte-Program mode. The default at power up is

Byte-Program mode.

©2006 Silicon Storage Technology, Inc.

7

S71264-02-000

1/06

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