SST25VF512A 데이터 시트보기 (PDF) - Silicon Storage Technology
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SST25VF512A Datasheet PDF : 25 Pages
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Data Sheet
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF512A. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
512 Kbit SPI Serial Flash
SST25VF512A
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
TABLE 6: DEVICE OPERATION INSTRUCTIONS1
Bus Cycle2
1
2
3
4
5
6
Cycle Type/Operation3,4 SIN SOUT SIN SOUT SIN SOUT
SIN
SOUT SIN SOUT
SIN
SOUT
Read (20 MHz)
03H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
Hi-Z X DOUT
High-Speed-Read (33 MHz) 0BH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z X
X
Sector-Erase5,6
20H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
Hi-Z -
-
X
DOUT
Block-Erase5,7
52H or Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
Hi-Z -
-
D8H
Chip-Erase6
60H or Hi-Z
-
-
-
-
-
-
-
-
C7H
Byte-Program6
02H Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
Hi-Z DIN Hi-Z
DIN
Hi-Z
Auto Address Increment
(AAI) Program6,8
AFH Hi-Z A23-A16 Hi-Z A15-A8 Hi-Z
A7-A0
Hi-Z DIN Hi-Z
DIN
Hi-Z
Read-Status-Register
(RDSR)
05H Hi-Z
X
DOUT
-
Note9
-
Note9 - Note9
Note9
Enable-Write-Status-Register 50H Hi-Z
-
-
-
-
-
-
-
-
(EWSR)10
Write-Status-Register
(WRSR)10
01H Hi-Z Data Hi-Z
-
-
-.
-
-
-
Write-Enable (WREN)
06H Hi-Z
-
-
-
-
-
-
-
-
Write-Disable (WRDI)
Read-ID
04H Hi-Z
-
-
-
-
-
-
-
-
90H or Hi-Z 00H Hi-Z 00H Hi-Z ID Addr11 Hi-Z X DOUT12
X
DOUT12
ABH
1. AMS = Most Significant Address
T6.0 1264
AMS = A15 for SST25VF512A
Address bits above the most significant bit of each density can be VIL or VIH
2. One bus cycle is eight clock periods.
3. Operation: SIN = Serial In, SOUT = Serial Out
4. X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use AMS-A12, remaining addresses can be VIL or VIH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN) instruction
must be executed.
7. Block addresses for: use AMS-A15, remaining addresses can be VIL or VIH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of
each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both
instructions effective.
11. Manufacturer’s ID is read with A0=0, and Device ID is read with A0=1. All other address bits are 00H. The Manufacturer’s and Device
ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 48H for SST25VF512A
©2006 Silicon Storage Technology, Inc.
8
S71264-02-000
1/06
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