SST25PF020B 데이터 시트보기 (PDF) - Microchip Technology

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SST25PF020B

2 Mbit 2.3-3.6V SPI Serial Flash

Microchip Technology 

SST25PF020B

CE#

MODE 3

SCK MODE 0

0 1 23456 78

15 16

23 24 31

SI

D8

ADDR ADDR ADDR

MSB

MSB

SO

HIGH IMPEDANCE

25135 63KBlkEr.0

FIGURE 4-12:

64-KBYTE BLOCK-ERASE SEQUENCE

4.5.9 CHIP-ERASE

The Chip-Erase instruction clears all bits in the device

to FFH. A Chip-Erase instruction will be ignored if any

of the memory area is protected. Prior to any Write oper-

ation, the Write-Enable (WREN) instruction must be exe-

cuted. CE# must remain active low for the duration of

the Chip-Erase instruction sequence. The Chip-Erase

instruction is initiated by executing an 8-bit command,

60H or C7H. CE# must be driven high before the instruction

is executed. The user may poll the Busy bit in the software

status register or wait TCE for the completion of the

internal self-timed Chip-Erase cycle. See Figure 4-13

for the Chip-Erase sequence.

CE#

MODE 3

SCK MODE 0

0 1 23456 7

SI

60 or C7

MSB

SO

HIGH IMPEDANCE

25135 ChEr.0

FIGURE 4-13:

CHIP-ERASE SEQUENCE

4.5.10 READ-STATUS-REGISTER (RDSR)

The Read-Status-Register (RDSR) instruction allows

reading of the status register. The Status Register may

be read at any time even during a Write (Program/

Erase) operation. When a Write operation is in prog-

ress, the Busy bit may be checked before sending any

new commands to assure that the new commands are

properly received by the device. CE# must be driven

low before the RDSR instruction is entered and remain

low until the status data is read. Read-Status-Register

is continuous with ongoing clock cycles until it is termi-

nated by a low to high transition of the CE#. See Figure

4-14 for the RDSR instruction sequence.

DS20005135B-page 14

 2013 Microchip Technology Inc.

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