SST39VF040-55-4I-MKE 데이터 시트보기 (PDF) - Silicon Storage Technology
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SST39VF040-55-4I-MKE
Silicon Storage Technology
SST39VF040-55-4I-MKE Datasheet PDF : 24 Pages
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512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040
SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040
AC CHARACTERISTICS
Data Sheet
TABLE 9: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for
SST39VF512/010/020/040
SST39LF512-45
SST39LF010-45
SST39LF020-45
SST39LF040-45
SST39LF020-55
SST39LF040-55
SST39VF512-70
SST39VF010-70
SST39VF020-70
SST39VF040-70
Symbol Parameter
Min
Max
Min
Max
Min
Max
Units
TRC
Read Cycle Time
45
55
70
ns
TCE
Chip Enable Access Time
45
55
70
ns
TAA
Address Access Time
45
55
70
ns
TOE
Output Enable Access Time
30
30
35
ns
TCLZ1 CE# Low to Active Output
0
0
0
ns
TOLZ1 OE# Low to Active Output
0
0
0
ns
TCHZ1 CE# High to High-Z Output
15
15
25
ns
TOHZ1 OE# High to High-Z Output
15
15
25
ns
TOH1
Output Hold from Address Change
0
0
0
ns
T9.2 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: Program/Erase Cycle Timing Parameters
Symbol Parameter
Min
Max
Units
TBP
Byte-Program Time
TAS
Address Setup Time
TAH
Address Hold Time
20
µs
0
ns
30
ns
TCS
TCH
TOES
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
0
ns
0
ns
0
ns
TOEH
TCP
TWP
TWPH1
TCPH1
TDS
TDH1
TIDA1
TSE
OE# High Hold Time
CE# Pulse Width
WE# Pulse Width
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
Data Hold Time
Software ID Access and Exit Time
Sector-Erase
10
ns
40
ns
40
ns
30
ns
30
ns
40
ns
0
ns
150
ns
25
ms
TSCE
Chip-Erase
100
ms
T10.1 1150
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2010 Silicon Storage Technology, Inc.
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01/10
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