SST39SF010A 데이터 시트보기 (PDF) - Silicon Storage Technology
부품명
상세내역
제조사
SST39SF010A Datasheet PDF : 25 Pages
| |||
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39SF010A / SST39SF020A / SST39SF040
Data Sheet
TABLE 5: DC Operating Characteristics VDD = 4.5-5.5V1
Limits
Symbol Parameter
Min
Max
Units Test Conditions
IDD
Power Supply Current
Read2
Program and Erase
ISB1
Standby VDD Current
(TTL input)
Address input=VILT/VIHT, at f=1/TRC Min
VDD=VDD Max
25
mA
CE#=VIL, OE#=WE#=VIH, all I/Os open
35
mA
CE#=WE#=VIL, OE#=VIH
3
mA
CE#=VIH, VDD=VDD Max
ISB2
Standby VDD Current
(CMOS input)
100
µA
CE#=VIHC, VDD=VDD Max
ILI
Input Leakage Current
1
µA
VIN=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
10
µA
VOUT=GND to VDD, VDD=VDD Max
VIL
Input Low Voltage
0.8
V
VDD=VDD Min
VIH
Input High Voltage
2.0
V
VDD=VDD Max
VIHC
Input High Voltage (CMOS)
VDD-0.3
V
VDD=VDD Max
VOL
Output Low Voltage
0.4
V
IOL=2.1 mA, VDD=VDD Min
VOH
Output High Voltage
2.4
V
IOH=-400 µA, VDD=VDD Min
1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C
(room temperature), and VDD = 5V for SF devices. Not 100% tested.
2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information.
T5.10 1147
TABLE 6: Recommended System Power-up Timings
Symbol
Parameter
Minimum
Units
TPU-READ1 Power-up to Read Operation
100
µs
TPU-WRITE1 Power-up to Program/Erase Operation
100
µs
T6.1 1147
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: Capacitance (Ta = 25°C, f=1 Mhz, other pins open)
Parameter Description
Test Condition
Maximum
CI/O1
I/O Pin Capacitance
VI/O = 0V
12 pF
CIN1
Input Capacitance
VIN = 0V
6 pF
T7.0 1147
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: Reliability Characteristics
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1,2
TDR1
Endurance
Data Retention
10,000
100
Cycles
Years
JEDEC Standard A117
JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA
JEDEC Standard 78
T8.2 1147
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a
higher minimum specification.
©2010 Silicon Storage Technology, Inc.
8
S71147-09-000
01/10
Share Link: 