2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
INTERNAL PROGRAM OPERATION STARTS
1
TBP
ADDRESS A17-0
5555
TAH
2AAA
5555 ADDR
2
TCP
TDH
CE#
TAS
TCPH
TDS
3
OE#
4
TCH
WE#
5
TCS
DQ7-0
AA
55
A0
DATA
6
SW0
SW1
SW2
BYTE
(ADDR/DATA)
326 ILL F05.3
7
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
8
9
ADDRESS A17-0
CE#
OE#
WE#
DQ7
TOEH
TCE
TOE
D
D#
10
11
TOES
12
13
14
D#
D
326 ILL F06.0
15
FIGURE 6: DATA# POLLING TIMING DIAGRAM
16
© 1998 Silicon Storage Technology, Inc.
11
326-10 12/98