SST39SF020-90-4I-P 데이터 시트보기 (PDF) - Silicon Storage Technology
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SST39SF020-90-4I-P Datasheet PDF : 23 Pages
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2 Megabit Multi-Purpose Flash
SST39SF020
Preliminary Specifications
Toggle Bit (DQ6)
or power-down. Any Erase operation requires the inclusion
During the internal Program or Erase operation, any con- of six byte load sequence. The SST39SF020 device is
secutive attempts to read DQ6 will produce alternating 0’s
and 1’s, i.e., toggling between 0 and 1. The Toggle Bit will
shipped with the software data protection permanently
enabled. See Table 4 for the specific software command
1
begin with “1”. When the internal Program or Erase opera- codes. During SDP command sequence, invalid com-
tion is completed, the toggling will stop. The device is then
ready for the next operation. The Toggle Bit is valid after the
mands will abort the device to read mode, within TRC.
2
rising edge of fourth WE# (or CE#) pulse for Program Product Identification
operation. For Sector or Chip Erase, the Toggle Bit is valid
after the rising edge of sixth WE# (or CE#) pulse. See
The product identification mode identifies the device as the
SST39SF020 and manufacturer as SST. This mode may
3
Figure 7 for Toggle Bit timing diagram and Figure 15 for a be accessed by hardware or software operations. The
flowchart.
hardware operation is typically used by a programmer to
identify the correct algorithm for the SST39SF020 device.
4
Data Protection
Users may wish to use the software product identification
The SST39SF020 device provides both hardware and operation to identify the part (i.e., using the device code)
software features to protect nonvolatile data from inadvert-
when using multiple manufacturers in the same socket. For
5
ent writes.
details, see Table 3 for hardware operation or Table 4 for
Hardware Data Protection
software operation, Figure 10 for the software ID entry and
read timing diagram and Figure 16 for the ID entry com-
6
Noise/Glitch Protection: A WE# or CE# pulse of less than mand sequence flowchart.
5 ns will not initiate a write cycle.
VCC Power Up/Down Detection: The write operation is
inhibited when VCC is less than 2.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Address
Manufacturer’s Code
0000H
Device Code
0001H
7
Data
BF H
B6 H
8
326 PGM T1.2
Software Data Protection (SDP)
Product Identification Mode Exit/Reset
9
In order to return to the standard read mode, the Software
The SST39SF020 provides the JEDEC approved soft- Product Identification mode must be exited. Exiting is
ware data protection scheme for all data alteration opera-
accomplished by issuing the Exit ID command sequence,
10
tions, i.e., Program and Erase. Any Program operation which returns the device to the Read operation. Please
requires the inclusion of a series of three byte sequence. note that the software reset command is ignored during an
The three byte-load sequence is used to initiate the Pro-
gram operation, providing optimal protection from inad-
internal Program or Erase operation. See Table 4 for
software command codes, Figure 11 for timing waveform
11
vertent write operations, e.g., during the system power-up and Figure 16 for a flowchart.
12
FUNCTIONAL BLOCK DIAGRAM OF SST39SF020
2,097,152 bit
13
X-Decoder
EEPROM
Cell Array
14
A17 - A0
Address Buffers & Latches
Y-Decoder
15
CE#
OE#
Control Logic
I/O Buffers and Data Latches
WE#
16
DQ7 - DQ0
326 ILL B1.3
© 1998 Silicon Storage Technology, Inc.
3
326-10 12/98
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