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SST39LF160 데이터 시트보기 (PDF) - Silicon Storage Technology

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SST39LF160
SST
Silicon Storage Technology SST
SST39LF160 Datasheet PDF : 26 Pages
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16 Mbit Multi-Purpose Flash
SST39LF160 / SST39VF160
Data Sheet
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V FOR SST39LF160 AND 2.7-3.6V FOR SST39VF160
Limits
Symbol Parameter
Min Max Units Test Conditions
IDD
ISB
IALP
ILI
ILO
VIL
VILC
VIH
VIHC
VOL
VOH
Power Supply Current
Read
Program and Erase
Standby VDD Current
Auto Low Power Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
Input High Voltage
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
20
25
20
20
1
10
0.8
0.3
0.7 VDD
VDD-0.3
0.2
VDD-0.2
Address input=VIL/VIH, at f=1/TRC Min.,
VDD=VDD Max.
mA CE#=OE#=VIL,WE#=VIH, all I/Os open
mA CE#=WE#=VIL, OE#=VIH
µA CE#=VIHC, VDD=VDD Max.
µA CE#=VIHC, VDD=VDD Max.,
all inputs = VIHC or VILC, WE#=VIHC
µA VIN=GND to VDD, VDD=VDD Max.
µA VOUT=GND to VDD, VDD=VDD Max.
V VDD=VDD Min.
V VDD=VDD Max.
V VDD=VDD Max.
V VDD=VDD Max.
V IOL=100 µA, VDD=VDD Min.
V IOH = -100 µA, VDD=VDD Min.
T8.3 399
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
TPU-WRITE1
Power-up to Program/Erase Operation
100
µs
T9.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
CI/O1
CIN1
I/O Pin Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
12 pF
6 pF
T10.0 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units Test Method
NEND1
Endurance
10,000
Cycles JEDEC Standard A117
TDR1
Data Retention
100
Years JEDEC Standard A103
ILTH1
Latch Up
100 + IDD
mA JEDEC Standard 78
T11.1 399
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
10
S71145-02-000 6/01 399

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