SST39VF160-70_98 데이터 시트보기 (PDF) - Silicon Storage Technology
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SST39VF160-70_98 Datasheet PDF : 23 Pages
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16 Megabit Multi-Purpose Flash
SST39VF160Q / SST39VF160
Advance Information
then ready for the next operation. During internal Erase Common Flash Memory Interface (CFI)
operation, any attempt to read DQ7 will produce a ‘0’. Once The SST39VF160Q/VF160 also contain the CFI informa-
the internal Erase operation is completed, DQ7 will pro-
duce a ‘1’. The Data# Polling is valid after the rising edge
tion to describe the characteristics of the device. In order
to enter the CFI query mode, the system must write 3 byte
1
of fourth WE# (or CE#) pulse for Program operation. For sequence, same as product ID entry command with 98H
Sector or Chip Erase, the Data# Polling is valid after the
rising edge of sixth WE# (or CE#) pulse. See Figure 6 for
(CFI query command) to address 5555H in the last byte
sequence. Once the device enters the CFI query mode, the
2
Data# Polling timing diagram and Figure 17 for a flowchart. system can read CFI data at the addresses given in tables
Toggle Bit (DQ6)
5 through 8. The system must write the reset command to
return to read mode from the CFI query mode.
3
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 1’s Product Identification
and 0’s, i.e., toggling between 1 and 0. The toggle bit will
The Product Identification mode identifies the devices as
4
begin with ‘1’. When the internal Program or Erase opera- the SST39VF160Q, SST39VF160 and manufacturer as
tion is completed, the DQ6 bit will stop toggling. The device SST. This mode may be accessed by hardware or soft-
is then ready for the next operation. The Toggle Bit is valid
ware operations. The hardware operation is typically used
5
after the rising edge of fourth WE# (or CE#) pulse for by a programmer to identify the correct algorithm for the
Program operation. For Sector or Chip Erase, the Toggle SST39VF160Q/VF160. Users may wish to use the soft-
Bit is valid after the rising edge of sixth WE# (or CE#) pulse.
ware product identification operation to identify the part
6
See Figure 7 for Toggle Bit timing diagram and Figure 18 (i.e., using the device code) when using multiple manufac-
for a flowchart.
turers in the same socket. For details, see Table 3 for
Data Protection
hardware operation or Table 4 for software operation,
7
Figure 9 for the software ID entry and read timing diagram
The SST39VF160Q/VF160 provide both hardware and and Figure 18 for the ID entry command sequence flow-
software features to protect nonvolatile data from inadvert-
ent writes.
chart.
TABLE 1: PRODUCT IDENTIFICATION TABLE
8
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
Manufacturer’s Code
Address
0000H
Data
00BFH
9
5 ns will not initiate a write cycle.
Device Code
0001H
2782H
VDD Power Up/Down Detection: The Write operation is
329 PGM T1.1
10
inhibited when VDD is less than 1.5V.
Product Identification Mode Exit/CFI Mode Exit
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
11
ent writes during power-up or power-down.
plished by issuing the Software Exit ID command se-
quence, which returns the device to the Read operation.
Software Data Protection (SDP)
This command may also be used to reset the device to the
12
The SST39VF160Q/VF160 provide the JEDEC approved
read mode after any inadvertent transient condition that
Software Data Protection scheme for all data alteration
apparently causes the device to behave abnormally, e.g.,
operations, i.e., Program and Erase. Any Program opera-
not read correctly. Please note that the software reset
13
tion requires the inclusion of the three byte sequence. The
command is ignored during an internal Program or Erase
three byte-load sequence is used to initiate the Program
operation. See Table 4 for software command codes,
operation, providing optimal protection from inadvertent
Figure 13 for timing waveform and Figure 18 for a flow-
14
Write operations, e.g., during the system power-up or
chart.
power-down. Any Erase operation requires the inclusion of
six byte sequence. The SST39VF160Q/VF160 device is
shipped with the software data protection permanently
VDDQ - I/O Power Supply
This feature is available only on the SST39VF160Q. This
15
enabled. See Table 4 for the specific software command pin functions as power supply pin for input/output buffers.
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode within TRC. The
It should be tied to VDD (2.7V - 3.6V) in a 3.0V-only system.
It should be tied to a 5.0V±10% (4.5V - 5.5V) power supply
16
contents of DQ15-DQ8 are “Don’t Care” during any SDP
in a mixed voltage system environment where flash
command sequence.
memory has to be interfaced with 5V system chips. The
VDDQ pin is not offered on the SST39VF160, instead it is a
No Connect pin.
© 1998 Silicon Storage Technology, Inc.
3
329-09 11/98
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