ST72C314N4T6(2003) 데이터 시트보기 (PDF) - STMicroelectronics

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ST72C314N4T6
(Rev.:2003)

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

STMicroelectronics 

ST72334J/N, ST72314J/N, ST72124J

2 INTRODUCTION

The ST72334J/N, ST72314J/N and ST72124J de-

vices are members of the ST7 microcontroller fam-

ily. They can be grouped as follows:

– ST72334J/N devices are designed for mid-range

applications with Data EEPROM, ADC, SPI and

SCI interface capabilities.

– ST72314J/N devices target the same range of

applications but without Data EEPROM.

– ST72124J devices are for applications that do

not need Data EEPROM and the ADC peripher-

al.

All devices are based on a common industry-

standard 8-bit core, featuring an enhanced instruc-

tion set.

The ST72C334J/N, ST72C314J/N and

ST72C124J versions feature single-voltage

FLASH memory with byte-by-byte In-Situ Pro-

gramming (ISP) capability.

Under software control, all devices can be placed

in WAIT, SLOW, ACTIVE-HALT or HALT mode,

reducing power consumption when the application

is in idle or standby state.

The enhanced instruction set and addressing

modes of the ST7 offer both power and flexibility to

software developers, enabling the design of highly

efficient and compact application code. In addition

to standard 8-bit data management, all ST7 micro-

controllers feature true bit manipulation, 8x8 un-

signed multiplication and indirect addressing

modes.

For easy reference, all parametric data are located

in Section 16 on page 107.

Figure 1. General Block Diagram

RESET

ISPSEL

VDD

VSS

OSC1

OSC2

PF7,6,4,2:0

(6-BIT)

PE7:0

(6-BIT for N versions)

(2-BIT for J versions)

8-BIT CORE

ALU

CONTROL

LVD

MULTI OSC

+

CLOCK FILTER

MCC/RTC

PORT F

TIMER A

BEEP

PORT E

SCI

WATCHDOG

PROGRAM

MEMORY

(8K or 16K Bytes)

RAM

(384 or 512 Bytes)

EEPROM

(256 Bytes)

PORT A

PORT B

PORT C

TIMER B

SPI

PORT D

8-BIT ADC

PA7:0

(8-BIT for N versions)

(5-BIT for J versions)

PB7:0

(8-BIT for N versions)

(5-BIT for J versions)

PC7:0

(8-BIT)

PD7:0

(8-BIT for N versions)

(6-BIT for J versions)

VDDA

VSSA

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