ST20184 데이터 시트보기 (PDF) - STMicroelectronics

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ST20184

ADSL, ADSL2 and ADSL+ Modem Chipset for CPE Applications with Utopia II Interface

STMicroelectronics 

ST20190

plementation risks. The data interface is implemented as an ATM Utopia interface. A HW/FW command

and control interface (CtrlE) to communicate with external management entities, is directly provided, with-

out need for glue logic.

The chipset employs Discrete Multi-Tone modulation as specified in ANSI T1.413. It also supports ETSI

TS 101 388 and ITU standards G.992.1 (G.dmt) including Annex A, B and C; G.992.2 (G.lite) annex A, B

and C; G.992.3 (ADSL2) including Annex A, B, C, I, J and L; G.992.5 (G.ADSL+) including Annex A, B, C,

I, J and Annex L.

Flexible bit assignment is foreseen to support ADSL overlay over POTS and ISDN but also All Digital loop

and overlapping spectra. Additional Reed-Solomon forward error correction with optional interleaving pro-

vides maximum noise immunity.

4 THE MODEM ENVIRONMENT

An integrated ADSL-compatible line driver is used to drive the telephone twisted pair, and a POTS/ISDN

splitter or adequate distributed filtering is required to split the baseband analogue telephone or ISDN sig-

nal from the modulated ADSL signal. In G.Lite mode, the splitter can be removed and replaced by distrib-

uted POTS filters. Brief characteristics of the system are given in Section 6. The bit rate can be varied in

steps of 32 kbits/s in ADSL and in steps of 1 kbit/s in ADSL2/ADSL+ mode.

Figure 2. Utopia Chipset Block Diagram

ATM

Management

Entity

Utopia I or II

ST20196

- DMT Modem

- ATM framer

- Microcontroller

Control

CtrlE

SDRAM

flash

EPROM

(Optional)

ST20184

Analog

Front End

~

Line

~

5 CHIPSET FUNCTIONS

The functions performed by each IC are as follows:

5.1 ST20184

This CMOS IC contains the analogue functions required in the transceiver. In order to cope with the high

attenuation of the line and in order to maintain an acceptable noise level of the signal, Programmable gain

amplifiers have been implemented at the analogue front of the transmission and reception paths. In Re-

ception, the signal goes through a LNA, a high pass filter to eliminate echo and LNA before a low pass

filter for anti-aliasing. The AD and DA converters provide 14-bit resolution at 2.2 MHz sampling rate.

Finally, for the transmission part, the control of the external hybrid driver is done by a highly integrated

linear line driver.

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