STE2004DIE1 데이터 시트보기 (PDF) - STMicroelectronics

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STE2004DIE1

102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

STMicroelectronics 

Figure 4. Master Slave Logic Connection with frame Synchronization

STE2004

STE2004

VDD1AUX OSCIN FRIN OSCOUT FROUT

STE2004

FRIN OSCIN

OSCOUT FROUT

LR0219

Figure 5. Master Slave Logic Connection without frame Synchronization

STE2004

STE2004

VDD1AUX OSCIN FRIN OSCOUT FROUT

OSCIN

OSCOUT FROUT

VDD1AUX

FRIN

LR0220

uct(s) 3.5 Bias Levels

rod To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated.

The ratios among these levels and VLCD, should be selected according to the MUX ratio (m). They are

P established to be (Fig. 6):

olete VLCD,

n-----+-----3--

n+4

VL

C

D

,

n-----+-----2--

n+4

VL

C

D

,

-----2-------

n+4

VL

C

D

,

-----1-------

n+4

VLCD ,VSS

Obs Figure 6. Bias level Generator

t(s) - R

VLCD

n+3

c n + 4 ·VLCD

uR

d n+2

n + 4 ·VLCD

ro nR

2

P n + 4 ·VLCD

te R

1

le n + 4 ·VLCD

R

so VSS D00IN1150

Obthus providing an 1/(n+4) ratio, with n calculated from:

n= m – 3

For m = 65, n = 5 and an 1/9 ratio is set.

For m = 49, n =4 and an 1/8 ratio is set.

The STE2004 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below:

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