STE2004DIE1 데이터 시트보기 (PDF) - STMicroelectronics
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STE2004DIE1 Datasheet PDF : 66 Pages
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STE2004
Table 3.
BS2
BS1
BS0
n
0
0
0
7
0
0
1
6
0
1
0
5
0
1
1
4
1
0
0
3
1
0
1
2
1
1
0
1
1
1
1
0
The following table Bias Level for m = 65 and m = 49 are provided:
Table 4.
Symbol
m = 65 (1/9)
m = 49 (1/8)
V1
VLCD
VLCD
V2
8/9*VLCD
7/8*VLCD
t(s) V3
7/9*VLCD
6/8*VLCD
V4
2/9*V VLCD
2/8*VLCD
uc V5
1/9 *VLCD
1/8*VLCD
d V6
VSS
VSS
Pro 3.6 LCD Voltage Generation
te The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to
le the following formula:
so VLCD(T=To) = VLCDo = (Ai+VOP · B) (i=0,1,2)
b with the following values:
O Symbol
) - Ao
t(s A1
c A2
u B
rod To
Value
2.95
6.83
10.71
0.0303
27
Unit
Note
V
PRS = [0;0]
V
PRS = [0;1]
V
PRS = [1;0]
V
°C
P Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits
are set to zero the internal voltage generator is switched off.
te The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Mul-
le tiplexing Rate. A general expression for this is:
Obso VLCD
=
---------1-----+---------m------------
2 ⋅ ⎝⎛1 – ----1-m---⎠⎞
⋅
Vth
For MUX Rate m = 65 the ideal VLCD is:
VLCD(to) = 6.85 · Vth
than:
Vop
=
(---6---.--8---5-----⋅---V----t--h----–-----A----i--)
0.03
8/66
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