STK14CA8-25 데이터 시트보기 (PDF) - Unspecified
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STK14CA8-25 Datasheet PDF : 17 Pages
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STK14CA8
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
1
tELQV
tACS
2
tAVAVc
tAVAVc
tRC
3
tAVQVd
tAA
4
tGLQV
tOE
5
tAXQXd
tOH
6
tELQX
tLZ
7
tEHQZe
tHZ
8
tGLQX
tOLZ
9
tGHQZe
tOHZ
10
tELICCb
tPA
11
tEHICCb
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Notes
c: W must be high during SRAM READ cycles
d: Device is continuously selected with E and G both low
e: Measured ± 200mV from steady state output voltage
f: HSB must remain high during READ and WRITE cycles.
STK14CA8-25
MIN
MAX
25
25
25
12
3
3
10
0
10
0
25
SRAM READ CYCLE #1: Address Controlledc,d,f
2
tAVAV
ADDRESS
DQ (DATA OUT)
5
tAXQX
3
tAVQV
DATA VALID
STK14CA8-35
MIN
MAX
35
35
35
15
3
3
13
0
13
0
35
STK14CA8-45
MIN
MAX
45
45
45
20
3
3
15
0
15
0
45
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SRAM READ CYCLE #2: E Controlledc,f
ADDRESS
E
6
tELQX
2
tAVAV
1
tELQV
G
DQ (DATA OUT)
ICC
8
tGLQX
10
tELICCH
STANDBY
4
tGLQV
ACTIVE
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
December 2005
5
Document Control #ML0022 rev 1.3
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