STK14C88-NF35U 데이터 시트보기 (PDF) - Simtek Corporation
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STK14C88-NF35U Datasheet PDF : 15 Pages
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STK14C88-NF35U
SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
tELQV
tACS
2
tAVAVg, tELEHg
tRC
3
tAVQVh
tAA
4
tGLQV
tOE
5
tAXQXh
tOH
6
tELQX
tLZ
7
tEHQZi
tHZ
8
tGLQX
9
tGHQZi
10
tELICCHf
11
tEHICCLf
tOLZ
tOHZ
tPA
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note g: W and HSB must be high during SRAM READ cycles.
Note h: I/O state assumes E and G < VIL and W > VIH; device is continuously selected.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
SRAM READ CYCLE #2: E and G Controlledg
(VCC = 5.0V ± 10%)e
STK14C88-NF35U
MIN
MAX
UNITS
35
ns
35
ns
35
ns
15
ns
5
ns
5
ns
13
ns
0
ns
13
ns
0
ns
35
ns
ADDR ESS
E
27
G
DQ (D ATA OUT)
ICC
6
tELQ X
2
tE LE H
1
tEL Q V
3
tAV QV
8
tG LQ X
4
tG L QV
10
tELI CC H
ST AND BY
AC T IVE
29
tEHAX
11
tEHI CC L
7
tEHQ Z
9
tGH Q Z
DAT A VAL ID
Document Control #ML0066 Rev 2.0
4
Feb, 2008
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