STK14C88-NF35U 데이터 시트보기 (PDF) - Simtek Corporation
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STK14C88-NF35U Datasheet PDF : 15 Pages
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SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
#1
#2
Alt.
PARAMETER
12
tAVAV
13
tWLWH
14
tELWH
15
tDVWH
16
tWHDX
17
tAVWH
18
tAVWL
19
tWHAX
20
t
WL
i,
QZ
j
21
tWHQX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
tWC
Write Cycle Time
tWP
Write Pulse Width
tCW
Chip Enable to End of Write
tDW
Data Set-up to End of Write
tDH
Data Hold after End of Write
tAW
Address Set-up to End of Write
tAS
Address Set-up to Start of Write
tWR
Address Hold after End of Write
tWZ
Write Enable to Output Disable
tOW
Output Active after End of Write
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12
tAVAV
ADDRESS
14
tELWH
E
W
DATA IN
DATA OUT
18
tAVWL
17
tAVWH
13
tWLWH
20
tWLQZ
PREVIOUS DATA
15
tDVWH
DATA VALID
HIGH IMPEDANCE
SRAM WRITE CYCLE #2: E Controlledk, l
ADDRESS
12
tAVAV
18
tAVEL
14
tELEH
E
STK14C88-NF35U
(VCC = 5.0V ± 10%)e
STK14C88-NF35U
MIN
MAX
35
25
25
12
0
25
0
0
13
5
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19
tWHAX
16
tWHDX
21
tWHQX
19
tEHAX
17
tAVEH
W
DATA IN
DATA OUT
Document Control #ML0066 Rev 2.0
Feb, 2008
13
tWLEH
15
tDVEH
DATA VALID
HIGH IMPEDANCE
5
16
tEHDX
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