STK15C88-45 데이터 시트보기 (PDF) - Unspecified
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STK15C88-45 Datasheet PDF : 9 Pages
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STK15C88
Internally, RECALL is a two step procedure. First,
the SRAM data is cleared and second, the nonvola-
tile information is transferred into the SRAM cells.
After the tRECALL cycle time the SRAM will once again
be ready for READ and WRITE operations. The
RECALL operation in no way alters the data in the
EEPROM cells. The nonvolatile data can be recalled
an unlimited number of times.
AutoStoreTM OPERATION
The STK15C88 uses the intrinsic system capaci-
tance to perform an automatic store on power
down. As long as the system power supply takes at
least tSTORE to decay from VSWITCH down to 3.6V the
STK15C88 will safely and automatically store the
SRAM data in EEPROM on power-down.
In order to prevent unneeded STORE operations,
automatic STORE will be ignored unless at least
one WRITE operation has taken place since the
most recent STORE or RECALL cycle. Software initi-
ated STORE cycles are performed regardless of
whether a WRITE operation has taken place.
POWER UP RECALL
During power up, or after any low power condition
(VCC < VRESET) an internal recall request will be
latched. When VCC once again exceeds the sense
voltage of V , SWITCH a RECALL cycle will automatically
be initiated and will take tRESTORE to complete.
HARDWARE PROTECT
The STK15C88 offers hardware protection against
inadvertent STORE operation during low voltage
conditions. When VCC < VSWITCH all Software STORE
operations will be inhibited.
LOW AVERAGE ACTIVE POWER
The STK15C88 draws significantly less current
when it is cycled at times longer than 30ns. Figure
2, below, shows the relationship between ICC and
READ cycle time. Worst case current consumption
is shown for both CMOS and TTL input levels (com-
mercial temperature range, VCC = 5.5V, 100% duty
cycle on chip enable). Figure 3 shows the same
relationship for WRITE cycles. If the chip enable
duty cycle is less than 100%, only standby current
is drawn when the chip is disabled. The overall
average current drawn by the STK15C88 depends
on the following items: 1) CMOS vs. TTL input lev-
els; 2) the duty cycle of chip enable; 3) the overall
cycle rate for accesses; 4) the ratio of READ’s to
WRITE’s; 5) the operating temperature; 6) the VCC
level and; 7) I/O loading.
100
80
60
40
20
TTL
CMOS
0
50 100 150 200
Cycle Time (ns)
Fig 2: Icc (max) Reads
100
80
60
TTL
40
CMOS
20
0
50 100 150 200
Cycle Time (ns)
Fig 3: Icc (Max) Writes
August 1998
5-42
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