STK16C88-3 데이터 시트보기 (PDF) - Cypress Semiconductor
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STK16C88-3 Datasheet PDF : 14 Pages
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STK16C88-3
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [11, 12]
Parameter
tRC
tSA[11]
tCW[11]
tHACE[7, 11]
tRECALL
Alt
tAVAV
tAVEL
tELEH
tELAX
Description
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
35 ns
Unit
Min
Max
35
ns
0
ns
25
ns
20
ns
20
μs
Switching Waveforms
Figure 10. CE Controlled Software STORE/RECALL Cycle [12]
ADDRESS
CE
OE
tRC
ADDRESS # 1
tSA
tSCE
tHACE
DQ (DATA)
DATA VALID
tRC
ADDRESS # 6
t / t STORE RECALL
HIGH IMPEDANCE
DATA VALID
Notes
11. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).
12. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.
Document Number: 001-50594 Rev. **
Page 11 of 14
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