MD82C288-10 데이터 시트보기 (PDF) - Intel

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MD82C288-10

BUS CONTROLLER FOR M80286 PROCESSORS

Intel 

M82C288

Bus State Definition

The M82C288 bus controller has three bus states

(see Figure 4) Idle (TI) Status (TS) and Command

(TC) Each bus state is two CLK cycles long Bus

state phases correspond to the internal CPU proces-

sor clock phases

The TI bus state occurs when no bus cycle is cur-

rently active on the M80286 local bus This state

may be repeated indefinitely When control of the

local bus is being passed between masters the bus

remains in the TI state

Bus Cycle Definition

The S1 and S0 inpus signal the start of a bus cycle

When either input becomes LOW a bus cycle is

started The TS bus state is defined to be the two

CLK cycles during which either S1 or S0 are active

(see Figure 5) These inputs are sampled by the

M82C288 at every falling edge of CLK When either

S1 and S0 are sampled LOW the next CLK cycle is

considered the second phase of the internal CPU

clock cycle

The local bus enters the TC bus state after the TS

state The shortest bus cycle may have one TS state

and one TC state Longer bus cycles are formed by

repeating TC state A repeated TC bus state is called

a wait state

The READY input determines whether the current

TC bus state is to be repeated The READY input

has the same timing and effect for all bus cycles

READY is sampled at the end of each TC bus state

to see if it is active If sampled HIGH The TC bus

state is repeated This is called inserting a wait state

The control and command outputs do not change

during wait states

When READY is sampled LOW the current bus cy-

cle is terminated Note that the bus controller may

enter the TS bus state directly from TC if the status

lines are sampled active at the next falling edge of

CLK

271077 –4

Figure 4 M82C288 Bus States

Figure 5 Bus Cycle Definition

271077 – 5

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