SX1504 데이터 시트보기 (PDF) - Semtech Corporation
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SX1504 Datasheet PDF : 33 Pages
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ADVANCED COMMUNICATIONS & SENSING
SX1504/SX1505/SX1506
4/8/16 Channel GPIO
Symbol Description
Conditions
Min
Typ
Max Unit
NRESET (Input/Output)
VOL Low level output voltage
-
-
-
0.3 V
IOLM Low level output sink current
VIHMR High level input voltage
-
-
-
12 mA
-
0.7*
VDDM
-
5.5 V
VILM Low level input voltage
-
-0.4
-
0.3*
VDDM
V
VHYSM Hysteresis of Schmitt trigger
-
-
0.1*
VDDM
-
V
ILEAK Input leakage current
-
-1.5
-
1.5 µA
CI Input capacitance
-
-
-
10 pF
VPOR Power-On-Reset voltage
Cf. Figure 7
0.7
-
0.9 V
VDROPH High brown-out voltage
Cf. Figure 7
-
VDDM-1
-
V
VDROPL Low brown-out voltage
Cf. Figure 7
-
0.2
-
V
tRESET Reset time
tPULSE Reset pulse from host uC
Cf. Figure 7
Cf. Figure 7
0.6
-
300
-
7 ms
-
ns
ADDR (Input)
VIHMA High level input voltage
-
0.7*
VDDM
-
VDDM
+0.3
V
VILM Low level input voltage
-
-0.4
-
0.3*
VDDM
V
VHYSM Hysteresis of Schmitt trigger
-
-
0.1*
VDDM
-
V
ILEAK Input leakage current
-
-1.5
-
1.5 µA
CI Input capacitance
-
-
-
10 pF
SCL (Input) and SDA (Input/Output) (2)
Interface complies with slave F/S mode I2C interface as described by Philips I2C specification version 2.1
dated January, 2000. Please refer to that document for more detailed I2C specifications.
VOL Low level output voltage
-
IOLM Low level output sink current
-
VIHMR High level input voltage
-
VILM Low level input voltage
-
fSCL
SCL clock frequency
-
tHD;STA
Hold time (repeated) START
condition
-
tLOW LOW period of the SCL clock
-
tHIGH HIGH period of the SCL clock
-
tSU;STA
Set-up time for a repeated
START condition
-
tHD;DAT Data hold time
-
tSU;DAT Data set-up time
-
tr
Rise time of both SDA and
SCL signals
-
tf
Fall time of both SDA and
SCL signals
-
tSU;STO
Set-up time for STOP
condition
-
Rev 1 – 3rd Oct. 2008
8
-
-
-
-
0.7*
VDDM
-
-0.4
-
0
-
0.6
-
1.3
-
0.6
-
0.6
-
0(3)
-
100(5)
-
20+0.1Cb(6)
-
20+0.1Cb(6)
-
0.6
-
0.3 V
12 mA
5.5 V
0.3*
VDDM
V
400 kHz
-
µs
-
µs
-
µs
-
µs
0.9(4) µs
-
300 ns
300 ns
-
µs
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