MT8843AS 데이터 시트보기 (PDF) - Mitel Networks

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MT8843AS

Calling Number Identification Circuit 2

Mitel Networks 

Preliminary Information

MT8843

Note that signals such as dual tone alert signal,

speech and DTMF tones lie in the same frequency

band as FSK. They will, therefore, be demodulated

and as a result, false data will be generated. To avoid

demodulation of false data, an FSKen pin is provided

so that the FSK demodulator may be disabled when

FSK signal is not expected.

The FSK characteristics described in Table 2 have

been specified in BT and Bellcore specifications. The

BT signal frequencies correspond to CCITT V.23. The

Bellcore frequencies correspond to Bell 202. CTA

requires that the TE be able to receive both CCITT

V.23 and Bell 202, as specified in the BT and Bellcore

specifications. CNIC2 is compatible with both formats

with no external intervention.

Item

BT

Bellcore

Mark

frequency

(logic 1)

1300Hz

± 1.5%

1200Hz

± 1%

Space

frequency

(logic 0)

Received

signal level -

mark

2100Hz

± 1.5%

-8dBV to

-40dBV

(-5.78dBm to

-37.78dBm)

2200Hz

± 1%

-12dBma to

-32dBm

Received

signal level -

space

Signal level

differential

(twist)

-8dBV to

-40dBV

up to 6dB

-12dBm to

-36dBm

up to 10dBb

Unwanted

signals

<= -20dB

(300-3400Hz)

<= -25dB

(200-3200Hz)c

Transmission

rate

1200 baud

± 1%

1200 baud

± 1%

Word format

1 start bit (logic

0), 8 bit word

(LSB first), 1 to

10 stop bits

(logic 1)

1 start bit (logic

0), 8 bit word

(LSB first),

1 stop bit

(logic 1)d

Table 2. FSK Characteristics

a. The signal power is expressed in dBm referenced to 600 ohm

at the CPE tip/ring (A/B) interface.

b. TR-NWT-000030, Bulletin No. 1

c. The frequency range is specified in TR-NWT-000030.

d. Up to 20 marks may be inserted in specific places in a single

or multiple data message.

CNIC2 will meet these characteristics with its input

op-amp at unity gain.

• 3-wire User Interface

The MT8843 provides a powerful dual mode 3-wire

interface so that the 8-bit data words in the

demodulated FSK bit stream can be extracted

without the need either for an external UART

(Universal Asynchronous Receiver Transmitter) or

for the TE/CPE’s microcontroller to perform the

UART function in software (asynchronous serial data

reception). The interface is specifically designed for

the 1200 baud rate and is comprised of the DATA,

DCLK (data clock) and DR (data ready) pins. Two

modes (modes 0 and 1) are selectable via control of

the device’s MODE pin: in mode 0, data transfer is

initiated by the CNIC2; in mode 1, data transfer is

initiated by the external microcontroller.

Mode 0

This mode is selected when the MODE pin is low. It

is the CNIC (MT8841) compatible mode where data

transfer is initiated by the device.

In this mode, CNIC2 receives the FSK signal,

demodulates it, and outputs the extracted data to the

DATA pin (refer to Figure 12). For each received stop

and start bit sequence, the CNIC2 outputs a fixed

frequency clock string of 8 pulses at the DCLK pin.

Each clock rising edge occurs in the centre of each

DATA bit cell. DCLK is not generated for the stop and

start bits. Consequently, DCLK will clock only valid

data into a peripheral device such as a serial to

parallel shift register or a micro-controller. CNIC2

also outputs an end of word pulse (data ready) at the

DR pin. The data ready signal indicates the reception

of every 10-bit word sent from the network to the TE/

CPE. This DR signal is typically used to interrupt a

micro-controller.

Mode 1

This mode is selected when the MODE pin is high. In

this mode, the microcontroller supplies read pulses

(DCLK) to shift the 8-bit data words out of the

MT8843, onto the DATA pin. CNIC2 asserts DR to

denote the word boundary and indicate to the

microprocessor that a new word has become

available (refer to Figure 14).

Internally, the MT8843’s demodulated data bits are

sampled and stored. After the 8th bit, the word is

parallel loaded into an 8 bit shift register and DR

goes low. The shift register’s contents are shifted out

to the DATA pin on DCLK’s rising edge in the order

they were received.

If DCLK begins while DR is low, DR will return to high

upon the first DCLK. This feature allows the

associated interrupt (see section on "Interrupt") to be

5-27

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