SY100ELT20V(1999) 데이터 시트보기 (PDF) - Micrel
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SY100ELT20V Datasheet PDF : 4 Pages
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5V/3.3V
TTL-to-DIFFERENTIAL
PECL TRANSLATOR
ClockWorks™
SY10ELT20V
SY100ELT20V
FEATURES
s 3.3V and 5V power supply options
s 300ps typical propagation delay
s Low power
s Differential PECL output
s PNP TTL input for minimal loading
s Flow-through pinouts
s Available in 8-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
NC 1
Q2
PECL
Q3
NC 4
8 VCC
TTL 7 D
6 NC
5 GND
SOIC
TOP VIEW
DESCRIPTION
The SY10/100ELT20V is a single TTL-to-differential
PECL translators. Because PECL (Positive ECL) levels
are used, either +5V or +3.3V and ground are required.
The small outline 8-lead SOIC package and low skew
single gate design make the ELT20V ideal for applications
that require the translation of a clock or data signal where
minimal space, low power, and low cost are critical.
The ELT20V is available in both ECL standards: the
10ELT is compatible with positive ECL 10H logic levels,
while the 100ELT is compatible with positive ECL 100K
logic levels.
PIN NAMES
Pin
Q
D
VCC
GND
Function
Differential PECL Output
TTL Input
+5V/+3.3V Supply
Ground
Rev.: A Amendment: /0
1
Issue Date: December 1999
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