SY69753L(2003) 데이터 시트보기 (PDF) - Micrel
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SY69753L Datasheet PDF : 9 Pages
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Micrel
PACKAGE/ORDERING INFORMATION
32 31 30 29 28 27 26 25
NC 1
RDINP 2
RDINN 3
NC 4
REFCLK 5
NC 6
NC 7
NC 8
Top View
EPAD-TQFP
H32-1
24 RDOUTP
23 RDOUTN
22 VCCO
21 RCLKP
20 RCLKN
19 VCCO
18 TCLKP
17 TCLKN
9 10 11 12 13 14 15 16
SY69753L
Ordering Information
Part Number
SY69753LHI
SY69753LHI*
*Tape and Reel
Package
Type
H32-1
H32-1
Operating
Range
Industrial
Industrial
Package
Marking
SY69753LHI
SY69753LHI
PIN DESCRIPTIONS
INPUTS
RDINP, RDINN [Serial Data Input] Differential PECL
These built-in line receiver inputs are connected to the
differential receive serial data stream. An internal receive PLL
recovers the embedded clock (RCLK) and data (RDOUT)
information.
REFCLK [Reference Clock] TTL Input
This input is used as the reference for the internal frequency
synthesizer and the "training" frequency for the receiver PLL to
keep it centered in the absence of data coming in on the RDIN
inputs.
CD [Carrier Detect] PECL Input
This input controls the recovery function of the Receive PLL
and can be driven by the carrier detect output of optical modules
or from external transition detection circuitry. When this input is
HIGH the input data stream (RDIN) is recovered normally by the
Receive PLL. When this input is LOW the data on the inputs
RDIN will be internally forced to a constant LOW, the data outputs
RDOUT will remain LOW, the Link Fault Indicator output LFIN
forced LOW and the clock recovery PLL forced to look onto the
clock frequency generated from REFCLK.
DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs
These inputs select the ratio between the output clock frequency
(RCLK/TCLK) and the REFCLK input frequency as shown in the
“Reference Frequency Selection” Table.
CLKSEL [Clock Select] TTL Inputs
This input is used to select either the recovered clock of the
receiver PLL (CLKSEL = HIGH) or the clock of the frequency
synthesizer (CLKSEL = LOW) to the TCLK outputs.
OUTPUTS
LFIN [Link Fault Indicator] TTL Output
This output indicates the status of the input data stream RDIN.
Active HIGH signal is indicating when the internal clock recovery
PLL has locked onto the incoming data stream. LFIN will go
HIGH if CD is HIGH and RDIN is within the frequency range of
the Receive PLL (1000ppm). LFIN is an asynchronous output.
RDOUTP, RDOUTN [Receive Data Output] Differential PECL
These ECL 100K outputs represent the recovered data from
the input data stream (RDIN). This recovered data is specified
against the rising edge of RCLK.
RCLKP, RCLKN [Clock Output] Differential PECL
These ECL 100K outputs represent the recovered clock used
to sample the recovered data (RDOUT).
TCLKP, TCLKN [Clock Output] Differential PECL
These ECL 100K outputs represent either the recovered clock
(CLKSEL = HIGH) used to sample the recovered data (RDOUT)
or the transmit clock of the frequency synthesizer
(CLKSEL = LOW).
PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]
External loop filter pins for the clock synthesis PLL.
PLLRP, PLLRN [Clock Recovery PLL Loop Filter]
External loop filter pins for the receiver PLL.
POWER & GROUND
VCC
VCCA
VCCO
GND
N/C
Supply Voltage(1)
Analog Supply Voltage(1)
Output Supply Voltage(1)
Ground
No Connect
NOTE:
1. VCC, VCCA, VCCO must be the same value.
2
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