SY69753L(2003) 데이터 시트보기 (PDF) - Micrel
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SY69753L Datasheet PDF : 9 Pages
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Micrel
SY69753L
FUNCTIONAL DESCRIPTION AND CHARACTERISTICS
Clock Recovery
Clock Recovery, as shown in the block diagram generates
a clock that is at the same frequency as the incoming data
bit rate at the Serial Data input. The clock is phase aligned
by a PLL so that it samples the data in the center of the
data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability without incoming data is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30µs data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
Lock Detect
The SY69753L contains a link fault indication circuit which
monitors the integrity of the serial data inputs. If the received
serial data fails the frequency test, the PLL will be forced to
lock to the local reference clock. This will maintain the correct
frequency of the recovered clock output under loss of signal
or loss of lock conditions. If the recovered clock frequency
deviates from the local reference clock frequency by more
than approximately 1000ppm, the PLL will be declared out
of lock. The lock detect circuit will poll the input data stream
in an attempt to reacquire lock to data. If the recovered
clock frequency is determined to be within approximately
1000ppm, the PLL will be declared in lock and the lock
detect output will go active.
Performance
The SY69753L PLL complies with the jitter specifications
proposed for SONET/SDH equipment defined by the Bellcore
Specifications: GR-253-CORE, Issue 2, December 1995 and ITU-
T Recommendations: G.958 document, when used with differential
inputs and outputs.
Input Jitter Tolerance
Input jitter tolerance is defined as the peak-to-peak amplitude
of sinusoidal jitter applied on the input signal that causes an
equivalent 1dB optical/electrical power penalty. SONET input jitter
tolerance requirement condition is the input jitter amplitude which
causes an equivalent of 1dB power penalty.
A
15
-20dB/decade
1.5
-20dB/decade
0.40
OC/STS-N
Level
3
f0 f1 f2
f4
ft
Frequency
f0
f1
f2
f3
ft
(Hz) (Hz) (Hz) (kHz) (kHz)
10
30
300
6.5
65
Figure 1. Input Jitter Tolerance
Jitter Transfer
Jitter transfer function is defined as the ratio of jitter on the
output OC-N/STS-N signal to the jitter applied on the input OC-N/
STS-N signal versus frequency. Jitter transfer requirements are
shown in Figure 2.
Jitter Generation
The jitter of the serial clock and serial data outputs shall not
exceed .01 U.I. rms when a serial data input with no jitter is
presented to the serial data inputs.
Jitter Transfer (dB)
0.1
-20
Acceptable
Range
-20dB/decade
OC/STS-N
Level
3
fc
fc
(kHz)
500
Frequency
P
(dB)
0.1
Figure 2. Jitter Transfer
5
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