LC7874E 데이터 시트보기 (PDF) - SANYO -> Panasonic

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LC7874E

CD Graphics Decorder

SANYO -> Panasonic 

LC7874E

Pin Functions

Pin Pin Symbol

Pin Name

1

S1

CD DSP selection pins

2

S2

3

SBCK Clock output pin

4

SFSY Sync signal input pin

5

PW

Data input pin

6

SBSY Sync signal input pin

7

VDD

Power supply pin (+5 v)

8

CE

Enable input pin

9

DO

Data output pin

10

DI

Data input pin

11

CL

Clock input pin

12 MUTE Data input pin

13

VSS

Ground pin (GND)

14

CB

Color bar selection pin

15 CDGM Graphic data discrimination output pin

16

CE1

DRAM control input pin

17

A0

DRAM output pin

18

A1

DRAM output pin

19

A2

DRAM output pin

20

A3

DRAM output pin

21

A4

DRAM output pin

22

A5

DRAM output pin

23

A6

DRAM output pin

24

A7

DRAM output pin

25

CAS

DRAM output pin

26

WE

DRAM output pin

27

OE

DRAM output pin

28

RAS

DRAM output pin

29

DB0

DRAM input/output pin

30

DB1

DRAM input/output pin

31

DB2

DRAM input/output pin

32

DB3

DRAM input/output pin

33 BLANK Blank signal output pin

34 CSYNC Composite sync output pin

I/O Polarity

Function

In Positive

S1 S2

Selected CD DSP

0

0 LC7861N/67

1

0 LC7860K/63

0

1 Setting prohibited

1

1 LC7868/62X/63X

Out

— Subcode R to W read clock output

In Positive Subcode frame sync signal input (MORE+ input)

In Positive Subcode R to W data input (MORE+ input)

In Positive Subcode block sync signal input (MORE+ input)

—

— Digital power supply

In Positive Serial input/output data control input (MORE+ input)

Out Positive Serial data output (Nch open-drain)

In Positive Serial data input (MORE+ input)

In Positive Serial data input/output clock input (MORE+ input)

In Positive Control signal input invalidating subcode data (MORE+ input)

—

— GND

In Positive L: Normal mode, H: Color bar output (built-in pull-down resistor)

Goes high when graphics data is input (can be reset low by command

Out Positive control).

Signal input setting DRAM connection pin to high impedance (MORE+

In Positive input)

I/O Positive DRAM address (A0) output

I/O Positive DRAM address (A1) output

I/O Positive DRAM address (A2) output

I/O Positive DRAM address (A3) output

I/O Positive DRAM address (A4) output

I/O Positive DRAM address (A5) output

I/O Positive DRAM address (A6) output

I/O Positive DRAM address (A7) output

3ST Negative DRAM column address strobe signal output

3ST Negative DRAM data write enable signal output

3ST Negative DRAM data read enable signal output

3ST Negative DRAM row address strobe signal output

I/O Positive DRAM data (D0) input/output

I/O Positive DRAM data (D1) input/output

I/O Positive DRAM data (D2) input/output

I/O Positive DRAM data (D3) input/output

3ST Positive Video signal blanking period output

3ST Negative Composite sync signal output

Continued on next page.

No. 5521-10/22

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