CXD1198AQ 데이터 시트보기 (PDF) - Sony Semiconductor
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CXD1198AQ Datasheet PDF : 51 Pages
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CXD1198AQ
4. Host DMA cycle (80-series bus)
(1) Read
HDRQ
XHAC
XHRD
HDB0 to 7
tDAR1
tSAR
tRRL
tDRD
Item
HDRQ fall time (vs. XHAC↓)
HDRQ rise time (vs. XHAC↑)
XHAC setup time (vs. XHRD↓)
XHAC hold time (vs. XHRD↑)
Low-level XHRD pulse width
Data delay time (vs. XHRD↓)
Data float time (vs. XHRD↑)
Symbol
tDAR1
tDAR2
tSAR
tHRA
tRRL
tDRD
tFRD
Min.
0
0
100
0
tHRA
tFRD
Typ.
tDAR2
Max.
Unit
35
ns
55
ns
ns
ns
ns
70
ns
ns
(2) Write
HDRQ
XHAC
XHWR
tDAR1
tSAW
HDB0 to 7
Item
HDRQ fall time (vs. XHAC↓)
HDRQ rise time (vs. XHAC↑)
XHAC setup time (vs. XHWR↓)
XHAC hold time (vs. XHWR↑)
Low-level XHWR pulse width
Data setup time (vs. XHWR↓)
Data float time (vs. XHWR↑)
tWWL
tSDW
tHWA
tHWD
tDAR2
Symbol Min.
Typ.
Max.
Unit
tDAR1
35
ns
tDAR2
55
ns
tSAW
0
ns
tHWA
0
ns
tWWL
50
ns
tSDW
40
ns
tHWD
10
ns
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