CXD1198AQ
3. Host interface
(1) Read
HA0 to 5
XHCS
XHRD
tSRC
tSRA
tRRL
tHRC
tHRA
HDB0 to 7
tDRD
tFRD
Item
Address setup time (vs. XHRD↓)
Chip select setup time (vs. XHRD↓)
Data delay time (vs. XHRD↓)
Data float time (vs. XHRD↑)
Chip select hold time (vs. XHRD↑)
Address hold time (vs. XHRD↑)
Low-level XHRD pulse width
Symbol Min.
Typ.
Max.
Unit
tSRA
20
ns
tSRC
0
ns
tDRD
70
ns
tFRD
2
ns
tHRC
0
ns
tHRA
0
ns
tRRL
100
ns
(2) Write
HA0 to 5
XHCS
XHWR
tSCW
tSAW
tWWL
tHWC
tHWA
HDB0 to 7
tSDW
tHWD
Item
Address setup time (vs. XHWR↓)
Chip select setup time (vs. XHWR↓)
Data setup time (vs. XHWR↓)
Data hold time (vs. XHWR↑)
Chip select hold time (vs. XHWR↑)
Address hold time (vs. XHWR↑)
Low-level XHWR pulse width
Symbol Min.
Typ.
Max.
Unit
tSAW
20
ns
tSCW
0
ns
tSDW
40
ns
tHWD
10
ns
tHWC
0
ns
tHWA
0
ns
tWWL
50
ns
—9—