CB45000 데이터 시트보기 (PDF) - STMicroelectronics

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CB45000

HCMOS6 STANDARD CELLS

STMicroelectronics 

Figure 8

SGS-THOMSON Layout Driven Design Flow

HARDWARE DESCRIPTION

LANGUAGE

VHDL / VERILOG

LOGIC SYNTHESIS

SCAN INSERTION

GATE LEVEL SIMULATION

VERILOG / MENTOR

TIMING ANALYSIS

FORMAL PROOF

ACCELERATION

HW / SW EMULATION

FAULT ANALYSIS

TSSI / IDDQ

CB45000 SERIES

FUNCTIONAL

SIMULATION

VHDL / VERILOG

SCHEMATIC CAPTURE

CADENCE

MENTOR

DELAY EVALUATION

RC BACK-ANNOTATION

POWER ESTIMATION

POWER ANALYSIS

CLOCK TREE SYNTHESIS

LAYOUT

SILICON

11/16

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