AT73C500 데이터 시트보기 (PDF) - Atmel Corporation
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AT73C500 Datasheet PDF : 28 Pages
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AT73C500
AT73C500 DSP
Figure 5. PLCC-44 package pin layout
IRQ0 /
GND SOUT1 SOUT0 PFAIL GND
GND
CLK STROBE VCC ADDR2 ADDR1
6
5
4
3
2
1 44 43 42 41 40
GND 7
39 ADDR0
B0 8
38 XRES
B1 9
37 BRDY
B2 10
36 RD/WR
GND 11
35 VCC
GND 12
34 GND
B12 13
33 SIN
B13 14
32 SCLK
B14 15
31 IRQ1 / ACK
GND 16
30 GND
B15 17
29 B11
18 19 20 21 22 23 24 25 26 27 28
B3
B4
GND
B5
B6
B7
N/C
B8
B9
GND B10
Power
Supply
Pins
VCC
GND
Pin
35, 42
1, 2, 6, 7,
11, 12,16,
20, 27, 30,
34
I/O
PWR
PWR
Description
Digital Supply, Positive, +5V
Digital Supply, Negative, 0V
Digital
Inputs
Pin
CLK
44
XRES
38
IRQ0
3
IRQ1
31
I/O Description
I Clock Input
I Reset Input, active low
Interrupt Input, usually
I connected to PFAIL output
of AT73C501
I
Interrupt Input, connected to
ACK Output of AT73C501
Status/
Mode
Bus
Pin
B15
17
B14
15
B13
14
B12
13
B11
29
B10
28
B9
26
B8
25
I/O Description
I/O Status/Mode Bus, Bit7
I/O Status/Mode Bus, Bit6
I/O Status/Mode Bus, Bit5
I/O Status/Mode Bus, Bit4
I/O Status/Mode Bus, Bit3
I/O Status/Mode Bus, Bit2
I/O Status/Mode Bus, Bit1
I/O Status/Mode Bus, Bit0
Microprocessor
Bus
Pin I/O
B7
23 I/O
B6
22 I/O
B5
21 I/O
B4
19 I/O
B3
18 I/O
B2
10 I/O
B1
9 I/O
B0
8 I/O
Description
µP Bus, Bit7
µP Bus, Bit6
µP Bus, Bit5
µP Bus, Bit4
µP Bus, Bit3
µP Bus, Bit2
µP Bus, Bit1
µP Bus, Bit0
AT73C501 /
AT73C502 and
EEPROM
Interface
SOUT0
SOUT1
SIN
SCLK
Pin I/O Description
4
O
Serial Output, used as a
clock for EEPROM
Serial Output, used as Chip
5
O
Select (CS) for AT73C501
and as Data Input (DI) for
EEPROM
33
I
Serial Data Input, data from
AT73C501 or from EEPROM
32
I
Serial Clock Input, bit clock
from AT73C501
Control Signals
of µP Bus and
Status/Mode
Bus
Pin I/O Description
STROBE
43 O Strobe Output
BRDY
37
I
Microprocessor ready for
I/O, Active Low
ADDR1
40
O
Address Output 1, used for
µP bus
ADDR0
Address Output 0, used for
39 O Status/ Mode bus and for
Impulse Outputs
RD/WR
36 O Read/Write Signal
5
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