M80C186 데이터 시트보기 (PDF) - Intel
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M80C186 Datasheet PDF : 59 Pages
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M80C186
FUNCTIONAL DESCRIPTION
Introduction
The following Functional Description describes the
base architecture of the M80C186 This architecture
is common to the M8086 M8088 M80186 and
M80286 microprocessor families as well The
M80C186 is a very high integration 16-bit microproc-
essor It combines 15– 20 of the most common mi-
croprocessor system components onto one chip
The M80C186 is object code compatible with the
M8086 M8088 microprocessors and adds 10 new
instruction types to the existing M8086 M8088 in-
struction set
The M80C186 has two major modes of operation
Compatible and Enhanced In Compatible Mode the
M80C186 is completely compatible with NMOS
M80186 with the exception of M8087 support All
pin functions timings and drive capabilities are
identical The Enhanced mode adds three new fea-
tures to the system design These are Power-Save
control Dynamic RAM refresh and an asynchro-
nous Numerics Co-processor interface
M80C186 BASE ARCHITECTURE
The M8086 M8088 M80186 and M80286 family all
contain the same basic set of registers instructions
and addressing modes The M80C186 processor is
upward compatible with the M8086 M8088 and
M80286 CPUs
Register Set
The M80C186 base architecture has fourteen regis-
ters as shown in Figures 3a and 3b These registers
are grouped into the following categories
these (AX BX CX and DX) can be used as 16-bit
registers or split into pairs of separate 8-bit registers
Segment Registers
Four 16-bit special purpose registers select at any
given time the segments of memory that are imme-
diately addressable for code stack and data (For
usage refer to Memory Organization )
Base and Index Registers
Four of the general purpose registers may also be
used to determine offset addresses of operands in
memory These registers may contain base address-
es or indexes to particular locations within a seg-
ment The addressing mode selects the specific reg-
isters for operand and address calculations
Status and Control Registers
Two 16-bit special purpose registers record or alter
certain aspects of the M80C186 processor state
These are the Instruction Pointer Register which
contains the offset address of the next sequential
instruction to be executed and the Status Word
Register which contains status and control flag bits
(see Figures 3a and 3b)
Status Word Description
The Status Word records specific characteristics of
the result of logical and arithmetic instructions (bits
0 2 4 6 7 and 11) and controls the operation of
the M80C186 within a given operating mode (bits 8
9 and 10) The Status Word Register is 16-bits wide
The function of the Status Word bits is shown in
Table 2
General Registers
Eight 16-bit general purpose registers may be used
to contain arithmetic and logical operands Four of
9
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