TDA10045 데이터 시트보기 (PDF) - Philips Electronics
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TDA10045 Datasheet PDF : 16 Pages
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Philips Semiconductors
Single Chip DVB-T Channel Receiver
Preliminary specification
TDA10045
,1387 287387 6,*1$/ '(6&5,37,21
SYMBOL PIN NUMBER TYPE
DESCRIPTION
CLOCK AND RESET SIGNALS
CLR#
14
I Asynchronous reset signal, active low
XIN
80
I
Crystal oscillator input pin. Typically a fundamental XTAL oscillator is
connected between XIN and XOUT.
XOUT
79
O Crystal oscillator output pin.
SACLK
33
O
(3.3V)
Sampling frequency output. This output clock can be fed to an external
(10-bit) ADC as sampling clock. Depending on “Sel_Saclk” (Reg
CONFADC), SACLK could also provide twice the sampling clock.
CTRL_VCXO
3
O If not in NCO mode, control of an external sampling VCXO (after low-
(3.3V) pass filtering)
DEMODULATOR SIGNALS
FI[9:0]
FFT_WIN
VAGC
FEL
IT
34-35-36-37-38- IO TRI Input data from an external ADC, FI must be tied to ground when not
41-42-43-44-45
used, positive notation (from 0 to 1023) or two's complement notation
(from -512 to 511). In internal ADC mode, these outputs can be used
to monitor extra demodulator output signal (constellation, frequency
response).
30
Output or input signal indicating the start of the active data; equals 1
IO TRI during complex sample 0 of the active FFT block. Can be used to
synchronize 2 chips.
4
O output value from the Delta-Sigma Modulator, used to control a log-
(3.3V) scaled amplifier (after analog filtering )
49
0D front end lock. FEL is an output drain output and therefore requires an
(5V) external pull up resistor.
48
OD
(5V)
Interrupt line. This output interrupt line can be configured by the I2C
interface. See registers Itsel and Itstat. IT is an open drain output and
therefore requires an external pull up resistor.
FEC OUTPUTS
DO[7:0]
OCLK
DEN
PSYNC
UNCOR
67-68-69-72-73-
74-75-76
66
65
64
63
O
(3.3V)
O
(3.3V)
O
(3.3V)
O
(3.3V)
O
(3.3V)
output data carrying the current sample of the current MPEG2 packet
(188 bytes), delivered on the rising edge of OCLK by default. When
the serial mode is selected, the output data is delivered by DO[0].
Output CLock. OCLK is the output clock for the parallel DO[7:0]
outputs. (may be inverted, see POCLK and DISABLE_TS I2C
registers)
output data validation signal active high during the valid and regular
data bytes (may be inverted, see PDEN and DISABLE_TS I2C
registers).
Pulse Synchro. This output signal goes high on a rising edge of OCLK
when a synchro byte is provided, then goes low until the next synchro
byte (may be inverted, see PPSYNC and DISABLE_TS I2C registers).
RS error flag, active high on one RS packet if the RS decoder fails in
correcting the errors (may be inverted, see PUNCOR and
DISABLE_TS I2C registers).
2000 March 15
4
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