TDA3605Q 데이터 시트보기 (PDF) - Philips Electronics

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TDA3605Q

Multiple voltage regulator with switch

Philips Electronics 

Philips Semiconductors

Multiple voltage regulator with switch

Preliminary specification

TDA3605Q

PINNING

SYMBOL PIN

DESCRIPTION

VP

REG1

1 supply voltage

2 regulator 1 output

REG3

3 regulator 3 output

Ven3

RES

4 enable input regulator 3

5 reset output voltage

Ven1

Ven(sw)

Vhold

VC

GND

6 enable input regulator 1

7 enable input power switch

8 hold output

9 reset delay capacitor

10 ground (0 V)

REG2

11 regulator 2 output

Vbu

12 back-up

Vsw

13 power switch output voltage

handbook, halfpage

VP 1

REG1 2

REG3 3

Ven3 4

RES 5

Ven1 6

Ven(sw) 7 TDA3605Q

Vhold 8

VC 9

GND 10

REG2 11

Vbu 12

Vsw 13

MGB752

Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

The TDA3605Q is a multiple output voltage regulator with

a power switch, intended for use in car radios with or

without a microcontroller. Because of low-voltage

operation of the car radio, low-voltage drop regulators are

used in the TDA3605Q.

Regulator 2 will switch-on when the back-up voltage

exceeds 6.5 V for the first time and will switch-off again

when the output voltage of regulator 2 is below 1.9 V

(this is far below an engine start). When regulator 2 is

switched on and the output voltage of this regulator is

within its voltage range, the reset output will be enabled

(reset will go HIGH via a pull-up resistor) to generate a

reset to the microcontroller. The reset cycles can be

extended by an external capacitor at pin 9. The above

mentioned start-up feature is built-in to secure a smooth

start-up of the microcontroller at first connection, without

uncontrolled switching of regulator 2 during the start-up

sequence.

The charge of the back-up capacitor can be used to supply

regulator 2 for a short period when the supply falls to 0 V

(time depends on value of storage capacitor). When both

regulator 2 and the supply voltage (VP > 4.5 V) are

available, regulators 1 and 3 can be operated by means of

enable inputs (pins 6 and 4 respectively).

Regulator 1 has a hold output (open collector) indicating

that the output voltage of this regulator is settled

(held HIGH by external pull-up resistor) and when the

output voltage of this regulator drops out of regulation

(because of supply voltage drop or high load) the hold

output will go LOW. The hold output signal is only valid

when regulator 1 is enabled by its enable input (pin 6).

The power switch can also be controlled by means of a

separate enable input (pin 7).

All output pins are fully protected. The regulators are

protected against load dump (regulator 1 and 3 will switch

off at supply voltages >18 V) and short-circuit (foldback

current protection).

The switch contains a current protection, but this

protection is delayed at short-circuit condition for at least

10 ms. During this time the output current is limited to a

peak value of at least 3 A and 2 A (DC) (VP ≤ 18 V).

At supply voltages >17 V the switch is clamped at

maximum 16 V (to avoid external connected circuitry being

damaged by an overvoltage) and the switch will switch-off

at load dump.

The total timing of a semi on/off logic set is shown in Fig.3.

1997 Jul 09

5

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