TDA6107JF 데이터 시트보기 (PDF) - Philips Electronics
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TDA6107JF Datasheet PDF : 20 Pages
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Philips Semiconductors
Triple video output amplifier
Product specification
TDA6107JF
Cathode output
The cathode output is protected against peak current
(caused by positive voltage peaks during high-resistance
flash) of 3 A maximum with a charge content of 100 µC (1).
The cathode is also protected against peak currents
(caused by positive voltage peaks during low-resistance
flash) of 6 A maximum with a charge content of 100 nC (1).
The DC voltage of VDD (pin 6) must be within the operating
range of 180 to 210 V during the peak currents.
Flashover protection
The TDA6107JF incorporates protection diodes against
CRT flashover discharges that clamp the cathodes output
voltage up to a maximum of VDD + Vdiode.
To limit the diode current an external 1.5 kΩ carbon
high-voltage resistor in series with the cathode output and
a 2 kV spark gap are needed (for this resistor value, the
CRT has to be connected to the main PCB (1).
VDD must be decoupled to GND:
1. With a capacitor >20 nF with good HF behaviour
(e.g. foil); this capacitor must be placed as close as
possible to pins 6 and 4, but definitely within 5 mm.
2. With a capacitor >3.3 µF on the picture tube base
print, depending on the CRT size.
Switch-off behaviour
The switch-off behaviour of the TDA6107JF is controllable.
This is because the output pins of the TDA6107JF are still
under control of the input pins for low power supply
voltages (approximately 30 V and higher).
Dissipation
Regarding dissipation, distinction must first be made
between static dissipation (independent of frequency) and
dynamic dissipation (proportional to frequency).
The static dissipation of the TDA6107JF is due to voltage
supply currents and load currents in the feedback network
and CRT.
The static dissipation Pstat equals:
Pstat = VDD × IDD + 3 × VOC × IOC
Where:
VDD = supply voltage
IDD = supply current
VOC = DC value of cathode voltage
IOC = DC value of cathode current.
The dynamic dissipation Pdyn equals:
Pdyn = 3 × VDD × (CL + Cint) × fi × Voc(p-p) × δ
Where:
CL = load capacitance
Cint = internal load capacitance (≈4 pF)
fi = input frequency
Voc(p-p) = output voltage (peak-to-peak value)
δ = non-blanking duty cycle.
The IC must be mounted on the picture tube base print to
minimize the load capacitance CL.
Bandwidth
The addition of the flash resistor produces a decreased
bandwidth and increases the rise and fall times; see
“Application Note AN96072”.
(1)External protection against higher currents is described
in “Application Note AN96072”.
2002 Oct 18
11
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