TDA6503 데이터 시트보기 (PDF) - Philips Electronics

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TDA6503

5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners

Philips Electronics 

Philips Semiconductors

5 V mixers/oscillators and synthesizers for

cable TV and VCR 2-band tuners

Product specification

TDA6502; TDA6502A;

TDA6503; TDA6503A

Table 8 Reference divider ratio select bits

RSA

X

0

1

RSB

0

1

1

REFERENCE DIVIDER RATIO

80

1 28

64

FREQUENCY STEP (kHz)

50

31.25

62.5

8.2.3 READ MODE

The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9).

After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is

transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data

byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge).

End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the

microcontroller to generate a STOP condition.

Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read

sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1)

A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC

information to the microcontroller of the IF section of the television.

Table 9 Read data format

NAME

BYTE

MSB(1)

Address byte

ADB

1

1

0

Status byte

SB

POR

FL

R

Note

1. MSB is transmitted first.

BIT

0

0

1

1

MA1

A2

MA0

A1

LSB

R/W = 1

A0

Table 10 Description of the bits used in Table 9

BIT

MA1 and MA0

R/W

POR

FL

R

A2, A1 and A0

DESCRIPTION

programmable address bits (see Table 6)

logic 1 for read mode

Power-on reset flag:

logic 0: after an end-of-data detected by the device

logic 1: at power-on

in-lock flag:

logic 0: loop is not locked

logic 1: loop is locked

ready flag:

logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked

logic 1: in other conditions

digital output of the 5-level ADC (see Table 11)

2001 Aug 22

11

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