TFRA08C13 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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TFRA08C13

OCTAL T1/E1 Framer

Agere -> LSI Corporation 

Preliminary Data Sheet

October 2000

TFRA08C13 OCTAL T1/E1 Framer

Table of Contents (continued)

Contents

Page

Receive Facility Data Link Interface.....................................................................................................................84

Transmit Facility Data Link Interface....................................................................................................................90

HDLC Operation ..................................................................................................................................................91

Transparent Mode................................................................................................................................................93

Diagnostic Modes ................................................................................................................................................95

Phase-Lock Loop Circuit .........................................................................................................................................96

Framer-System Interface ........................................................................................................................................98

DS1 Modes ..........................................................................................................................................................98

CEPT Modes........................................................................................................................................................98

Receive Elastic Store...........................................................................................................................................98

Transmit Elastic Store..........................................................................................................................................98

Concentration Highway Interface ............................................................................................................................98

CHI Parameters ...................................................................................................................................................99

CHI Frame Timing..............................................................................................................................................101

CHI Offset Programming....................................................................................................................................104

JTAG Boundary-Scan Specification ..................................................................................................................... 105

Principle of the Boundary Scan..........................................................................................................................105

Test Access Port Controller ...............................................................................................................................107

Instruction Register ............................................................................................................................................109

Boundary-Scan Register....................................................................................................................................110

BYPASS Register ..............................................................................................................................................110

DCODE Register................................................................................................................................................110

3-State Procedures ............................................................................................................................................110

Microprocessor Interface.......................................................................................................................................111

Overview ............................................................................................................................................................111

Microprocessor Configuration Modes ................................................................................................................111

Microprocessor Interface Pinout Definitions ......................................................................................................112

Microprocessor Clock (MPCLK) Specifications .................................................................................................112

Microprocessor Interface Register Address Map ...............................................................................................113

I/O Timing ..........................................................................................................................................................113

Reset.................................................................................................................................................................... 118

Hardware Reset (Pin C19).................................................................................................................................118

Software Reset/Software Restart.......................................................................................................................118

Interrupt Generation ..............................................................................................................................................118

Register Architecture.............................................................................................................................................119

Global Register Architecture .................................................................................................................................123

Global Register Structure......................................................................................................................................123

Framer Block Interrupt Status Register (GREG0)..............................................................................................123

Framer Block Interrupt Enable Register (GREG1).............................................................................................124

FDL Block Interrupt Status Enable Register (GREG2) ......................................................................................124

FDL Block Interrupt Enable Register (GREG3) .................................................................................................124

Global Control Register (GREG4)......................................................................................................................125

Device ID and Version Registers (GREG5—GREG7) .......................................................................................125

Global Control Register (GREG8)......................................................................................................................126

Global PLLCK Control Register (GREG9) .........................................................................................................127

Framer Register Architecture ................................................................................................................................127

Framer Status/Counter Registers ......................................................................................................................128

Framer Parameter/Control Registers .................................................................................................................141

FDL Register Architecture.....................................................................................................................................168

FDL Parameter/Control Registers ((A00—A0E); (A20—A2E); (B00—B0E);

(B20—B2E) (C00—C0E); (C20—C2E); (D00—D0E); (D20—D2E)) .................................................................169

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