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SAA7157

Clock signal generator circuit for digital TV systems (SCGC)

Philips Electronics 

Philips Semiconductors

Clock signal generator circuit for digital TV

systems (SCGC)

Product specification

SAA7157

CREF output

TV2 digital clock reference output signal. Clock qualifier signal to TV system with 2 times of LFCO or LFCO2 frequency.

Power-on reset

Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is

done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied

to reset other circuits of this digital TV system.

The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH.

PINNING

SYMBOL PIN DESCRIPTION

MS

CE

PORD

VSSA

VDDA

VSSD1

LL1.5A

VDDD1

VSSD2

LL1.5B

LFCO

RESN

VSSD3

LL3A

CREF

LFCOSEL

VDDD2

VSSD4

LFCO2

LL3B

1 mode select input (LOW = PLL mode)

2 chip enable /reset (HIGH = outputs enabled)

3 power-on reset delay, dependent on external capacitor

4 analog ground (0 V)

5 analog supply voltage (+5 V)

6 digital ground 1 (0 V)

7 line-locked clock output signal 1.5A (4 times fLFCO)

8 digital supply voltage 1 (+5 V)

9 digital ground 2 (0 V)

10 line-locked clock output signal 1.5B (4 times fLFCO)

11 line-locked frequency control input signal 1

12 reset output (active-LOW, Fig.4)

13 digital ground 3 (0 V)

14 line-locked clock output signal 3A (2 times fLFCO)

15 clock reference output, qualifier signal (2 times fLFCO)

16 LFCO source select (LOW = LFCO selected) (1)

17 digital supply voltage 2 (+5 V)

18 digital ground 4 (0 V)

19 line-locked frequency control input signal 2(1)

20 line-locked clock output signal 3B (2 times fLFCO)

Note

1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency.

May 1992

4

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